Datasheet

Analog to Digital Wrapper LogicAnalog to Digital Core
Input Circuit
Reference Voltage Levels
SOC
Arbitration
& Control
SOCx (0-15)
ADCIN0
Converter
ADCIN1
ADCIN2
ADCIN3
ADCIN4
ADCIN5
ADCIN6
ADCIN7
Interrupt Block (1-4)
Triggers
ADCIN8
ADCIN9
ADCIN10
ADCIN11
0
1
2
3
4
5
6
7
8
9
10
11
VREFLO
VREFHI
CHSEL
ADCSOC
[15:0]
ADCINT1-4
14
15
12
13
ADCIN12
ADCIN13
ADCIN14
ADCIN15
TRIGSEL
ACQPS
CHSEL
RESOLUTION
SIGNALMODE
Post Processing Block (1-4)
[15:0]
SIGNALMODE
RESOLUTION
RESULT
ADCRESULT
0–15 Regs
ADCPPBxRESULT
Event
Logic
ADCEVTINT
[15:0]
.
.
.
.
.
.
ADCEVT
TRIGGER[15:0]
Trigger
Timestamp
SOC Delay
Timestamp
ADCCOUNTER
ADCPPBxOFFCAL
ADCPPBxOFFREF
S
+
-
saturate
S
+
-
SOCxSTART[15:0]
EOCx[15:0]
CONFIG
u
1
x
2
x
1
S/H Circuit
V
IN
+
V
IN-
D
OUT
97
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
Figure 5-30 shows the ADC module block diagram.
Figure 5-30. ADC Module Block Diagram