Datasheet

86
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 5-40. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
(continued)
NO. PARAMETER MIN MAX UNIT
9 t
h(EMOEH-EMAIV)
Output hold time, EMxOE high to
EMxA[y:0] invalid
(RH)*E–3 (RH)*E ns
10 t
w(EMOEL)
EMxOE active low width (EW = 0) (RST)*E–1 (RST)*E+1 ns
EMxOE active low width (EW = 1) (RST+(EWC*16))*E–1 (RST+(EWC*16))*E+1 ns
11 t
d(EMWAITH-EMOEH)
Delay time from EMxWAIT
deasserted to EMxOE high
4E+10 5E+15 ns
29 t
su(EMDQMV-EMOEL)
Output setup time, EMxDQM[y:0]
valid to EMxOE low
(RS)*E–3 (RS)*E+2 ns
30 t
h(EMOEH-EMDQMIV)
Output hold time, EMxOE high to
EMxDQM[y:0] invalid
(RH)*E–3 (RH)*E ns
Writes
15 t
c(EMWCYCLE)
EMIF write cycle time (EW = 0) (WS+WST+WH+2)*E–3 (WS+WST+WH+2)*E+1 ns
EMIF write cycle time (EW = 1)
(WS+WST+WH+2+
(EWC*16))*E–3
(WS+WST+WH+2+
(EWC*16))*E+1
ns
16 t
su(EMCEL-EMWEL)
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 0)
(WS)*E–3 (WS)*E+1 ns
Output setup time, EMxCS[y:2] low
to EMxWE low (SS = 1)
–3 1 ns
17 t
h(EMWEH-EMCEH)
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 0)
(WH)*E–3 (WH)*E ns
Output hold time, EMxWE high to
EMxCS[y:2] high (SS = 1)
–3 0 ns
18 t
su(EMDQMV-EMWEL)
Output setup time, EMxDQM[y:0]
valid to EMxWE low
(WS)*E–3 (WS)*E+1 ns
19 t
h(EMWEH-EMDQMIV)
Output hold time, EMxWE high to
EMxDQM[y:0] invalid
(WH)*E–3 (WH)*E ns
20 t
su(EMBAV-EMWEL)
Output setup time, EMxBA[y:0]
valid to EMxWE low
(WS)*E–3 (WS)*E+1 ns
21 t
h(EMWEH-EMBAIV)
Output hold time, EMxWE high to
EMxBA[y:0] invalid
(WH)*E–3 (WH)*E ns
22 t
su(EMAV-EMWEL)
Output setup time, EMxA[y:0] valid
to EMxWE low
(WS)*E–3 (WS)*E+1 ns
23 t
h(EMWEH-EMAIV)
Output hold time, EMxWE high to
EMxA[y:0] invalid
(WH)*E–3 (WH)*E ns
24 t
w(EMWEL)
EMxWE active low width
(EW = 0)
(WST)*E–1 (WST)*E+1 ns
EMxWE active low width
(EW = 1)
(WST+(EWC*16))*E–1 (WST+(EWC*16))*E+1 ns
25 t
d(EMWAITH-EMWEH)
Delay time from EMxWAIT
deasserted to EMxWE high
4E+10 5E+15 ns
26 t
su(EMDV-EMWEL)
Output setup time, EMxD[y:0] valid
to EMxWE low
(WS)*E–3 (WS)*E+1 ns
27 t
h(EMWEH-EMDIV)
Output hold time, EMxWE high to
EMxD[y:0] invalid
(WH)*E–3 (WH)*E ns