Datasheet
85
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
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SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.7.9.3 EMIF Electrical Data and Timing
5.7.9.3.1 Asynchronous RAM
Table 5-39 shows the EMIF asynchronous memory timing requirements. Table 5-40 shows the EMIF
asynchronous memory switching characteristics. Figure 5-21 through Figure 5-24 show the EMIF
asynchronous memory timing diagrams.
(1) Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended
wait states. Figure 5-22 and Figure 5-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-39. EMIF Asynchronous Memory Timing Requirements
NO. MIN MAX UNIT
Reads and Writes
E EMIF clock period t
c(SYSCLK)
ns
2 t
w(EM_WAIT)
Pulse duration, EMxWAIT assertion and
deassertion
2E ns
Reads
12 t
su(EMDV-EMOEH)
Setup time, EMxD[y:0] valid before EMxOE high 15 ns
13 t
h(EMOEH-EMDIV)
Hold time, EMxD[y:0] valid after EMxOE high 0 ns
14 t
su(EMOEL-EMWAIT)
Setup Time, EMxWAIT asserted before end of
Strobe Phase
(1)
4E+20 ns
Writes
28 t
su(EMWEL-EMWAIT)
Setup Time, EMxWAIT asserted before end of
Strobe Phase
(1)
4E+20 ns
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait
Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],
WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more
information.
(2) E = EMxCLK period in ns.
(3) EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. The
maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more information.
Table 5-40. EMIF Asynchronous Memory Switching Characteristics
(1)(2)(3)
NO. PARAMETER MIN MAX UNIT
Reads and Writes
1 t
d(TURNAROUND)
Turn around time (TA)*E–3 (TA)*E+2 ns
Reads
3 t
c(EMRCYCLE)
EMIF read cycle time (EW = 0) (RS+RST+RH+2)*E–3 (RS+RST+RH+2)*E+2 ns
EMIF read cycle time (EW = 1)
(RS+RST+RH+2+
(EWC*16))*E–3
(RS+RST+RH+2+
(EWC*16))*E+2
ns
4 t
su(EMCEL-EMOEL)
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 0)
(RS)*E–3 (RS)*E+2 ns
Output setup time, EMxCS[y:2] low
to EMxOE low (SS = 1)
–3 2 ns
5 t
h(EMOEH-EMCEH)
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 0)
(RH)*E–3 (RH)*E ns
Output hold time, EMxOE high to
EMxCS[y:2] high (SS = 1)
–3 0 ns
6 t
su(EMBAV-EMOEL)
Output setup time, EMxBA[y:0]
valid to EMxOE low
(RS)*E–3 (RS)*E+2 ns
7 t
h(EMOEH-EMBAIV)
Output hold time, EMxOE high to
EMxBA[y:0] invalid
(RH)*E–3 (RH)*E ns
8 t
su(EMAV-EMOEL)
Output setup time, EMxA[y:0] valid
to EMxOE low
(RS)*E–3 (RS)*E+2 ns