Datasheet
80
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 5-35 shows the HALT mode timing requirements, Table 5-36 shows the switching characteristics,
and Figure 5-19 shows the timing diagram for HALT mode.
(1) For applications using X1/X2 for OSCCLK, the user must characterize their specific oscillator start-up time as it is dependent on
circuit/layout external to the device. See Table 5-17 for more information. For applications using INTOSC1 or INTOSC2 for OSCCLK,
see Section 5.7.3.5 for t
oscst
. Oscillator start-up time does not apply to applications using a single-ended crystal on the X1 pin, as it is
powered externally to the device.
Table 5-35. HALT Mode Timing Requirements
MIN MAX UNIT
t
w(WAKE-GPIO)
Pulse duration, GPIO wake-up signal
(1)
t
oscst
+ 2t
c(OSCCLK)
cycles
t
w(WAKE-XRS)
Pulse duration, XRS wake-up signal
(1)
t
oscst
+ 8t
c(OSCCLK)
cycles
(1) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
Table 5-36. HALT Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
d(IDLE-XCOS)
Delay time, IDLE instruction executed to XCLKOUT stop 16t
c(INTOSC1)
cycles
t
d(WAKE-HALT)
Delay time, external wake signal end to CPU1 program
execution resume
cycles
• Wakeup from flash
– Flash module in active state
75t
c(OSCCLK)
• Wakeup from flash
– Flash module in sleep state
17500t
c(OSCCLK)
(1)
• Wakeup from RAM
75t
c(OSCCLK)