Datasheet

78
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Table 5-33 shows the STANDBY mode timing requirements, Table 5-34 shows the switching
characteristics, and Figure 5-18 shows the timing diagram for STANDBY mode.
(1) QUALSTDBY is a 6-bit field in the LPMCR register.
Table 5-33. STANDBY Mode Timing Requirements
MIN MAX UNIT
t
w(WAKE-INT)
Pulse duration, external
wake-up signal
QUALSTDBY = 0 | 2t
c(OSCCLK)
3t
c(OSCCLK)
cycles
QUALSTDBY > 0 |
(2 + QUALSTDBY)t
c(OSCCLK)
(1)
(2 + QUALSTDBY) * t
c(OSCCLK)
(1) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(2) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
Table 5-34. STANDBY Mode Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
d(IDLE-XCOS)
Delay time, IDLE instruction executed to
XCLKOUT stop
16t
c(INTOSC1)
cycles
t
d(WAKE-STBY)
Delay time, external wake signal to
program execution resume
(1)
cycles
• Wakeup from flash
– Flash module in active state
175t
c(SYSCLK)
+ t
w(WAKE-INT)
• Wakeup from flash
– Flash module in sleep state
6700t
c(SYSCLK)
(2)
+ t
w(WAKE-INT)
• Wakeup from RAM
3t
c(OSC)
+ 15t
c(SYSCLK)
+
t
w(WAKE-INT)