Datasheet
WAKE
(A)
XCLKOUT
Address/Data
(internal)
t
w(WAKE)
t
d(WAKE-IDLE)
77
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com
SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.7.8.3 Low-Power Mode Wakeup Timing
Table 5-31 shows the IDLE mode timing requirements, Table 5-32 shows the switching characteristics,
and Figure 5-17 shows the timing diagram for IDLE mode.
(1) For an explanation of the input qualifier parameters, see Table 5-26.
Table 5-31. IDLE Mode Timing Requirements
(1)
MIN MAX UNIT
t
w(WAKE)
Pulse duration, external wake-up signal
Without input qualifier 2t
c(SYSCLK)
cycles
With input qualifier 2t
c(SYSCLK)
+ t
w(IQSW)
(1) For an explanation of the input qualifier parameters, see Table 5-26.
(2) This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered
by the wake-up signal) involves additional latency.
(3) This value is based on the flash power-up time, which is a function of the SYSCLK frequency, flash wait states (RWAIT), and
FPAC1[PSLEEP]. For more information, see the Flash and OTP Power-Down Modes and Wakeup section of the TMS320F2837xS
Delfino Microcontrollers Technical Reference Manual. This value can be realized when SYSCLK is 200 MHz, RWAIT is 3, and
FPAC1[PSLEEP] is 0x860.
Table 5-32. IDLE Mode Switching Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
t
d(WAKE-IDLE)
Delay time, external wake signal to program execution resume
(2)
cycles
• Wakeup from Flash
– Flash module in active state
Without input qualifier 40t
c(SYSCLK)
With input qualifier 40t
c(SYSCLK)
+ t
w(WAKE)
• Wakeup from Flash
– Flash module in sleep state
Without input qualifier 6700t
c(SYSCLK)
(3)
With input qualifier 6700t
c(SYSCLK)
(3)
+ t
w(WAKE)
• Wakeup from RAM
Without input qualifier 25t
c(SYSCLK)
With input qualifier 25t
c(SYSCLK)
+ t
w(WAKE)
A. WAKE can be any enabled interrupt, WDINT or XRS. After the IDLE instruction is executed, a delay of five OSCCLK
cycles (minimum) is needed before the wake-up signal could be asserted.
Figure 5-17. IDLE Entry and Exit Timing Diagram