Datasheet

Interrupt Vector
XINT1, XINT2, XINT3,
XINT4, XINT5
Address bus
(internal)
t
w(INT)
t
d(INT)
75
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.7.7.1 External Interrupt (XINT) Electrical Data and Timing
Table 5-27 lists the external interrupt timing requirements. Table 5-28 lists the external interrupt switching
characteristics. Figure 5-16 shows the external interrupt timing.
(1) For an explanation of the input qualifier parameters, see Table 5-26.
Table 5-27. External Interrupt Timing Requirements
(1)
MIN MAX UNIT
t
w(INT)
Pulse duration, INT input low/high
Synchronous 2t
c(SYSCLK)
cycles
With qualifier t
w(IQSW)
+ t
w(SP)
+ 1t
c(SYSCLK)
cycles
(1) For an explanation of the input qualifier parameters, see Table 5-26.
(2) This assumes that the ISR is in a single-cycle memory.
Table 5-28. External Interrupt Switching Characteristics
(1)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
d(INT)
Delay time, INT low/high to interrupt-vector fetch
(2)
t
w(IQSW)
+ 14t
c(SYSCLK)
t
w(IQSW)
+ t
w(SP)
+ 14t
c(SYSCLK)
cycles
Figure 5-16. External Interrupt Timing