Datasheet

INPUTXBAR4
CPU1.WDINT
CPU1.LPMINT
CPU1.WAKEINT
CPU1.TINT0
CPU1.
ePIE
INPUTXBAR13
INPUTXBAR5
INPUTXBAR6
INPUTXBAR14
GPIO0
GPIO1
...
...
GPIOx
CPU1.TIMER0
CPU1.XINT1 Control
CPU1.XINT5 Control
CPU1.XINT3 Control
CPU1.XINT4 Control
CPU1.XINT2 Control
Input
X-BAR
LPM Logic
CPU1.WD
INT13
INT14
NMI
CPU1
INT1
to
INT12
CPU1.TINT1
CPU1.TIMER1
CPU1.TINT2
CPU1.TIMER2
CPU1.TINT2
CPU1.NMIWD
Peripherals
74
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.7.7 Interrupts
Figure 5-15 provides a high-level view of the interrupt architecture.
As shown in Figure 5-15, the devices support five external interrupts (XINT1 to XINT5) that can be
mapped onto any of the GPIO pins.
In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU
interrupt groups, with 16 interrupts per group.
Figure 5-15. External and ePIE Interrupt Sources