Datasheet
GPIO Signal
1
Sampling Window
1 1 1 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 0 0
SYSCLK
(A)
GPxQSELn = 1,0 (6 samples)
(D)
Output From
Qualifier
QUALPRD = 1
(SYSCLK/2)
t
w(IQSW)
t
w(SP)
(SYSCLK cycle * 2 * QUALPRD) * 5
(C)
Sampling Period determined
by GPxCTRL[QUALPRD]
(B)
72
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) "n" represents the number of qualification samples as defined by GPxQSELn register.
(2) For t
w(GPI)
, pulse width is measured from V
IL
to V
IL
for an active low signal and V
IH
to V
IH
for an active high signal.
5.7.6.2 GPIO - Input Timing
Table 5-26 shows the general-purpose input timing requirements. Figure 5-13 shows the sampling mode.
Table 5-26. General-Purpose Input Timing Requirements
MIN MAX UNIT
t
w(SP)
Sampling period
QUALPRD = 0 1t
c(SYSCLK)
cycles
QUALPRD ≠ 0 2t
c(SYSCLK)
* QUALPRD cycles
t
w(IQSW)
Input qualifier sampling window t
w(SP)
* (n
(1)
– 1) cycles
t
w(GPI)
(2)
Pulse duration, GPIO low/high
Synchronous mode 2t
c(SYSCLK)
cycles
With input qualifier t
w(IQSW)
+ t
w(SP)
+ 1t
c(SYSCLK)
cycles
A. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It
can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLK cycle. For any other value "n",
the qualification sampling period in 2n SYSCLK cycles (that is, at every 2n SYSCLK cycles, the GPIO pin will be
sampled).
B. The qualification period selected through the GPxCTRL register applies to groups of 8 GPIO pins.
C. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is
used.
D. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLK cycles or
greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLK cycles. This would ensure
5 sampling periods for detection to occur. Because external signals are driven asynchronously, an 13-SYSCLK-wide
pulse ensures reliable recognition.
Figure 5-13. Sampling Mode