Datasheet

3
TCK
TDO
TDI/TMS
2
4
1
1a 1b
70
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.7.5.1 JTAG Electrical Data and Timing
Table 5-23 lists the JTAG timing requirements. Table 5-24 lists the JTAG switching characteristics.
Figure 5-11 shows the JTAG timing.
Table 5-23. JTAG Timing Requirements
NO. MIN MAX UNIT
1 t
c(TCK)
Cycle time, TCK 66.66 ns
1a t
w(TCKH)
Pulse duration, TCK high (40% of t
c
) 26.66 ns
1b t
w(TCKL)
Pulse duration, TCK low (40% of t
c
) 26.66 ns
3
t
su(TDI-TCKH)
Input setup time, TDI valid to TCK high 13 ns
t
su(TMS-TCKH)
Input setup time, TMS valid to TCK high 13 ns
4
t
h(TCKH-TDI)
Input hold time, TDI valid from TCK high 7 ns
t
h(TCKH-TMS)
Input hold time, TMS valid from TCK high 7 ns
Table 5-24. JTAG Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
2 t
d(TCKL-TDO)
Delay time, TCK low to TDO valid 6 25 ns
Figure 5-11. JTAG Timing