Datasheet

62
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.7.3.2.2 Internal Clock Frequencies
Table 5-12 provides the clock frequencies for the internal clocks.
(1) Lower LSPCLK will reduce device power consumption. The default at reset is SYSCLK/4.
(2) For SYSCLK above 100 MHz, the EPWMCLK must be half of SYSCLK.
Table 5-12. Internal Clock Frequencies
MIN NOM MAX UNIT
f
(SYSCLK)
Frequency, device (system) clock 2 200 MHz
t
c(SYSCLK)
Period, device (system) clock 5 500 ns
f
(PLLRAWCLK)
Frequency, system PLL output (before SYSCLK
divider)
120 400 MHz
f
(AUXPLLRAWCLK)
Frequency, auxiliary PLL output (before AUXCLK
divider)
120 400 MHz
f
(AUXPLL)
Frequency, AUXPLLCLK 60 60 MHz
f
(PLL)
Frequency, PLLSYSCLK 2 200 MHz
f
(LSP)
Frequency, LSPCLK
(1)
2 200 MHz
t
c(LSPCLK)
Period, LSPCLK 5 500 ns
f
(OSCCLK)
Frequency, OSCCLK (INTOSC1 or INTOSC2 or
XTAL or X1)
See respective clock MHz
f
(EPWM)
Frequency, EPWMCLK
(2)
100 MHz
f
(HRPWM)
Frequency, HRPWMCLK 60 100 MHz
5.7.3.2.3 Output Clock Frequency and Switching Characteristics
Table 5-13 provides the frequency of the output clock. Table 5-14 shows the switching characteristics of
the output clock, XCLKOUT.
Table 5-13. Output Clock Frequency
MIN MAX UNIT
f
(XCO)
Frequency, XCLKOUT 50 MHz
(1) A load of 40 pF is assumed for these parameters.
(2) H = 0.5t
c(XCO)
Table 5-14. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
(1)(2)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
t
f(XCO)
Fall time, XCLKOUT 5 ns
t
r(XCO)
Rise time, XCLKOUT 5 ns
t
w(XCOL)
Pulse duration, XCLKOUT low H – 2 H + 2 ns
t
w(XCOH)
Pulse duration, XCLKOUT high H – 2 H + 2 ns