Datasheet

61
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.7.3.2 Clock Frequencies, Requirements, and Characteristics
This section provides the frequencies and timing requirements of the input clocks, PLL lock times,
frequencies of the internal clocks, and the frequency and switching characteristics of the output clock.
5.7.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
Table 5-7 shows the frequency requirements for the input clocks. Table 5-16 shows the crystal equivalent
series resistance requirements. Table 5-8 shows the X1 input level characteristics when using an external
clock source. Table 5-9 and Table 5-10 show the timing requirements for the input clocks. Table 5-11
shows the PLL lock times for the Main PLL and the USB PLL.
Table 5-7. Input Clock Frequency
MIN MAX UNIT
f
(XTAL)
Frequency, X1/X2, from external crystal or resonator 10 20 MHz
f
(X1)
Frequency, X1, from external oscillator (PLL enabled) 2 20 MHz
Frequency, X1, from external oscillator (PLL disabled) 2 100 MHz
f
(AUXI)
Frequency, AUXCLKIN, from external oscillator 2 60 MHz
Table 5-8. X1 Input Level Characteristics When Using an External Clock Source (Not a Crystal)
over recommended operating conditions (unless otherwise noted)
PARAMETER MIN MAX UNIT
X1 V
IL
Valid low-level input voltage –0.3 0.3 * V
DDIO
V
X1 V
IH
Valid high-level input voltage 0.7 * V
DDIO
V
DDIO
+ 0.3 V
Table 5-9. X1 Timing Requirements
MIN MAX UNIT
t
f(X1)
Fall time, X1 6 ns
t
r(X1)
Rise time, X1 6 ns
t
w(X1L)
Pulse duration, X1 low as a percentage of t
c(X1)
45% 55%
t
w(X1H)
Pulse duration, X1 high as a percentage of t
c(X1)
45% 55%
Table 5-10. AUXCLKIN Timing Requirements
MIN MAX UNIT
t
f(AUXI)
Fall time, AUXCLKIN 6 ns
t
r(AUXI)
Rise time, AUXCLKIN 6 ns
t
w(AUXL)
Pulse duration, AUXCLKIN low as a percentage of t
c(XCI)
45% 55%
t
w(AUXH)
Pulse duration, AUXCLKIN high as a percentage of t
c(XCI)
45% 55%
(1) The PLL lock time here includes the two required PLL lock sequences. Cycle count includes code execution of the PLL initialization
routine, which could vary depending on compiler optimizations and flash wait states.
Table 5-11. PLL Lock Times
MIN NOM MAX UNIT
t
(PLL)
Lock time, Main PLL (X1, from external oscillator) 50 µs + 2500 * t
c(OSCCLK)
(1)
µs
t
(USB)
Lock time, USB PLL (AUXCLKIN, from external oscillator) 50 µs + 2500 * t
c(OSCCLK)
(1)
µs