Datasheet
6
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Revision History Copyright © 2014–2016, Texas Instruments Incorporated
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from October 22, 2015 to May 6, 2016 (from B Revision (October 2015) to C Revision) Page
• Global: Restructured document. ................................................................................................... 1
• Section 1.3 (Description): Removed paragraph about Configurable Logic Block (CLB). ................................... 2
• Table 3-1 (Device Comparison): TMS320F28375SPZP is available in the Q temperature range. ....................... 7
• Section 3.1 (Related Products): Added section. ................................................................................. 9
• Table 4-1 (Signal Descriptions): Updated DESCRIPTION of V
REFHIA
, V
REFHIB
, V
REFHIC
, V
REFHID
, and V
DDA
. ............ 16
• Figure 5-7 (Clocking System): Changed figure title from "Device Clocking" to "Clocking System." ..................... 60
• Table 5-19 (Flash Wait States): Changed title from "Minimum Required Flash Wait States at Different
Frequencies" to "Flash Wait States." Updated table............................................................................ 66
• Section 5.7.5.1 (JTAG Electrical Data and Timing): Added section. ........................................................ 70
• Table 5-39 (EMIF Asynchronous Memory Timing Requirements): Parameter 14 [t
su(EMOEL-EMWAIT)
]: Changed MIN
value from 4E to 4E+20............................................................................................................. 85
• Table 5-39: Parameter 28 [t
su(EMWEL-EMWAIT)
]: Changed MIN value from 4E to 4E+20. ..................................... 85
• Table 5-40 (EMIF Asynchronous Memory Switching Characteristics): Parameter 11 [t
d(EMWAITH-EMOEH)
]: Changed
MIN value from 3E+8 to 4E+10. Changed MAX value from 4E+10 to 5E+15............................................... 85
• Table 5-40: Parameter 25 [t
d(EMWAITH-EMWEH)
]: Changed MIN value from 3E+8 to 4E+10. Changed MAX value
from 4E+10 to 5E+15. .............................................................................................................. 85
• Section 5.9.4 (High-Resolution Pulse Width Modulator (HRPWM)): Removed NOTE about dual-edge high-
resolution being enabled. ........................................................................................................ 129
• Figure 5-67 (SPI CPU Interface): Changed figure title from "SPI" to "SPI CPU Interface." ............................. 151
• Table 5-80 (SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3): Parameter 2
[t
w(SPCH)M
, clock polarity = 0]: Updated MIN value and MAX value. ......................................................... 154
• Table 5-80: Parameter 3 [t
w(SPCL)M
, clock polarity = 0]: Updated MIN value and MAX value. ........................... 154
• Table 5-82 (SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3): Parameter 2
[t
w(SPCL)M
, clock polarity = 1]: Updated MIN value and MAX value. ......................................................... 157
• Table 5-82: Parameter 3 [t
w(SPCH)M
, clock polarity = 1]: Updated MIN value and MAX value. .......................... 157
• Table 5-86 (High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3):
Parameter 2 [t
w(SPCH)M
, clock polarity = 0]: Updated MIN value and MAX value. ......................................... 162
• Table 5-86: Parameter 3 [t
w(SPCL)M
, clock polarity = 0]: Updated MIN value and MAX value. ........................... 162
• Table 5-88 (High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3):
Parameter 2 [t
w(SPCL)M
, clock polarity = 1]: Updated MIN value and MAX value. ......................................... 165
• Table 5-88: Parameter 3 [t
w(SPCH)M
, clock polarity = 1]: Updated MIN value and MAX value. .......................... 165
• Section 6.1 (Overview): Removed paragraph about Configurable Logic Block (CLB). .................................. 176
• Table 6-5 (Peripheral Registers Memory Map): Added PROTECTED column and associated footnote. ............. 181
• Table 6-8 (Device Identification Registers): Added UID_UNIQUE. ........................................................ 186
• Section 6.14 (Configurable Logic Block (CLB)): Updated section. ......................................................... 197
• Section 7.1 (TI Design or Reference Design): Added section. .............................................................. 198
• Section 8 (Device and Documentation Support): Updated and restructured section. ................................... 199
• Section 8.2 (Tools and Software): Added section. ........................................................................... 200
• Section 8.3 (Documentation Support): Updated section. .................................................................... 202
• Section 9.1 (Packaging Information): Updated section. ...................................................................... 204