Datasheet
XRS
£100 nF
2.2 k – 10 kW W
V
DDIO
56
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.7 System
5.7.1 Power Sequencing
An external power supply must be used to supply 3.3 V to V
DDIO
, V
DD3VFL
, V
DDOSC
, and V
DDA
and to
provide 1.2 V to V
DD
. The internal VREG is not supported; therefore, the VREGENZ pin must be tied high
to 3.3 V. The supplies should ramp to full rail within 10 ms. Table 5-3 shows the supply ramp rate.
Table 5-3. Supply Ramp Rate
MIN MAX UNIT
Supply ramp rate V
DDIO
, V
DD
, V
DDA
, V
DD3VFL
, V
DDOSC
with respect to V
SS
330 10
5
V/s
The voltage on V
DDIO
should be greater than V
DD
or no less than 0.3 V below V
DD
at all times. V
DDIO
,
V
DD3VFL
, V
DDOSC
, and V
DDA
should be powered up together and be kept within 0.3 V of each other during
operation. Before powering the device, no voltage larger than 0.3 V above V
DDIO
should be applied to any
digital pin, and no voltage larger than 0.3 V above V
DDA
should be applied to any analog pin.
An internal power-on-reset (POR) circuit holds the device in reset and keeps the I/Os in a high-impedance
state during power up. External supply voltage supervisors (SVS) can be used to monitor the voltage on
the 3.3-V and 1.2-V rails and drive XRS low should supplies fall outside operational specifications.
5.7.2 Reset Timing
XRS is the device reset pin. It functions as an input and open-drain output. The device has a built-in
power-on reset (POR). During power up, the POR circuit drives the XRS pin low. A watchdog or NMI
watchdog reset also drives the pin low. An external circuit may drive the pin to assert a device reset.
A resistor with a value from 2.2 kΩ to 10 kΩ should be placed between XRS and V
DDIO
. A capacitor should
be placed between XRS and V
SS
for noise filtering; the capacitance should be 100 nF or smaller. These
values will allow the watchdog to properly drive the XRS pin to V
OL
within 512 OSCCLK cycles when the
watchdog reset is asserted. Figure 5-4 shows the recommended reset circuit.
Figure 5-4. Reset Circuit