Datasheet

16-/12-bit ADC
x4
ADC
Result
Regs
Peripheral Frame 1
GPIO MUX, Input X-BAR, Output X-BAR
Secure Memories
shown in Red
CPU1 Buses
Comparator
Subsystem
(CMPSS)
DAC
x3
Config
Data Bus
Bridge
ePWM-1/../12
eCAP-
1/../6
eQEP-1/2/3
HRPWM-1/../8
SDFM-1/2
EXTSYNCIN
EXTSYNCOUT
TZ1-TZ6
ECAPx
EQEPxA
EQEPxB
EPWMxA
EPWMxB
EQEPxI
EQEPxS
SDx_Dy SDx_Cy
SCI-
A/B/C/D
(16L FIFO)
I2C-A/B
(16L FIFO)
Data Bus Bridge
SCITXDx
SCIRXDx
SDAx
SCLx
CAN-
A/B
(32-MBOX)
Data Bus
Bridge
CANRXx
CANTXx
Data Bus
Bridge
USBDP
USBDM
USB
Ctrl /
PHY
GPIO
Data Bus
Bridge
GPIOn
EMIF1
Data Bus
Bridge
EM1Dx
EM1Ax
EM1CTLx
EMIF2
Data Bus
Bridge
EM2Dx
EM2Ax
EM2CTLx
A
D
B
C
JTAG
AUXCLKIN
External Crystal or
Oscillator
Watchdog
Main PLL
Aux PLL
INTOSC1
INTOSC2
Low-Power
Mode Control
GPIO MUX
TRST
TCK
TDI
TMS
TDO
MEMCPU1
Global Shared
16x 4Kx16
GS0-GS15 RAMs
CPU1.CLA1 Bus
C28 CPU-1
CPU Timer 0
CPU Timer 1
CPU Timer 2
ePIE
(up to 192
interrupts)
WD Timer
NMI-WDT
CPU1.CLA1 Data ROM
(4Kx16)
CPU1.CLA1 to CPU1
128x16 MSG RAM
CPU1 to CPU1.CLA1
128x16 MSG RAM
Boot-ROM 32Kx16
Nonsecure
Secure-ROM 32Kx16
Secure
CPU1.M0 RAM 1Kx16
CPU1.M1 RAM 1Kx16
CPU1.D0 RAM 2Kx16
CPU1.D1 RAM 2Kx16
CPU1 Local Shared
6x 2Kx16
LS0-LS5 RAMs
CPU1.CLA1
CPU1.DMA
PSWD
Dual
Code
Security
Module
+
Emulation
Code
Security
Logic
(ECSL)
PUMP
Flash Bank 0
256K x 16
Secure
(F28377S, F23875S only)
256K x 16
Secure
Flash Bank 1
User-Configurable
DCSM
OTP
1K x 16
(F28377S, F28375S only)
Flash Wrapper for
Bank 1
Flash Wrapper for
Bank 0
FPU
VCU-II
TMU
Analog
MUX
A5:0
B5:0
C5:2
ADCIN14
ADCIN15
D5:0
Peripheral Frame 2
SPI-
A/B/C
(16L FIFO)
SPISIMOx
SPISOMIx
SPICLKx
SPISTEx
McBSP-A/B
MDXx
MRXx
MCLKXx
MCLKRx
MFSXx
MFSRx
UPPAD[7:0]
UPPACLK
UPPAEN
UPPAWT
UPPAST
uPP
RAM
Copyright © 2016, Texas Instruments Incorporated
4
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Device Overview Copyright © 2014–2016, Texas Instruments Incorporated
1.4 Functional Block Diagram
Figure 1-1 shows the CPU system and associated peripherals.
Figure 1-1. Functional Block Diagram