Datasheet
34
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Terminal Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated
Table 4-1. Signal Descriptions (continued)
TERMINAL
I/O/Z
(1)
DESCRIPTION
NAME
MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
NO CONNECT
NC H4 – –
No connect. BGA ball is electrically open and not
connected to the die.
JTAG
TCK V15 81 50 I JTAG test clock with internal pullup (see Section 5.5)
TDI W13 77 46 I
JTAG test data input (TDI) with internal pullup. TDI is
clocked into the selected register (instruction or data) on
a rising edge of TCK.
TDO W15 78 47 O/Z
JTAG scan out, test data output (TDO). The contents of
the selected register (instruction or data) are shifted out
of TDO on the falling edge of TCK.
(3)
TMS W14 80 49 I
JTAG test-mode select (TMS) with internal pullup. This
serial control input is clocked into the TAP controller on
the rising edge of TCK.
TRST V14 79 48 I
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is driven low, the
device operates in its functional mode, and the test reset
signals are ignored. NOTE: TRST must be maintained
low at all times during normal device operation. An
external pulldown resistor is required on this pin. The
value of this resistor should be based on drive strength
of the debugger pods applicable to the design. A 2.2-kΩ
or smaller resistor generally offers adequate protection.
The value of the resistor is application-specific. TI
recommends that each target board be validated for
proper operation of the debugger and the application.
This pin has an internal 50-ns (nominal) glitch filter.
INTERNAL VOLTAGE REGULATOR CONTROL
VREGENZ J18 119 64 I
Internal voltage regulator enable with internal pulldown.
To enable the 1.2-V VREG, pull low to V
SS
. To disable,
pull high to V
DDIO
.
ANALOG, DIGITAL, AND I/O POWER
V
DD
E9 16 16
1.2-V digital logic power pins. If the internal 1.2-V VREG
is used, place a decoupling capacitor near each V
DD
pin
and distribute 12 µF to 26 µF evenly across all V
DD
pins.
If an external supply is used, TI recommends a minimum
total capacitance of 20 µF. The exact value of the
decoupling capacitance should be determined by your
system voltage regulation solution.
E11 21 39
F9 61 45
F11 76 63
G14 117 71
G15 126 78
J14 137 84
J15 153 89
K5 158 95
K6 169 –
P10 – –
P13 – –
R10 – –
R13 – –
V
DD3VFL
R11 72 41
3.3-V Flash power pin. Place a minimum 0.1-µF
decoupling capacitor on each pin.
R12 – –
V
DDA
P6 36 18
3.3-V analog power pins. Place a minimum 2.2-µF
decoupling capacitor to V
SSA
on each pin.
R6 54 38