Datasheet
33
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Terminal Configuration and FunctionsCopyright © 2014–2016, Texas Instruments Incorporated
Table 4-1. Signal Descriptions (continued)
TERMINAL
I/O/Z
(1)
DESCRIPTION
NAME
MUX
POSITION
ZWT
BALL
NO.
PTP
PIN
NO.
PZP
PIN
NO.
GPIO156 0, 4, 8, 12
D12 – –
I/O General-purpose input/output 156
EPWM6B 1 O Enhanced PWM6 output B (HRPWM-capable)
GPIO157 0, 4, 8, 12
B10 – –
I/O General-purpose input/output 157
EPWM7A 1 O Enhanced PWM7 output A (HRPWM-capable)
GPIO158 0, 4, 8, 12
C10 – –
I/O General-purpose input/output 158
EPWM7B 1 O Enhanced PWM7 output B (HRPWM-capable)
GPIO159 0, 4, 8, 12
D10 – –
I/O General-purpose input/output 159
EPWM8A 1 O Enhanced PWM8 output A (HRPWM-capable)
GPIO160 0, 4, 8, 12
B9 – –
I/O General-purpose input/output 160
EPWM8B 1 O Enhanced PWM8 output B (HRPWM-capable)
GPIO161 0, 4, 8, 12
C9 – –
I/O General-purpose input/output 161
EPWM9A 1 O Enhanced PWM9 output A
GPIO162 0, 4, 8, 12
D9 – –
I/O General-purpose input/output 162
EPWM9B 1 O Enhanced PWM9 output B
GPIO163 0, 4, 8, 12
A8 – –
I/O General-purpose input/output 163
EPWM10A 1 O Enhanced PWM10 output A
GPIO164 0, 4, 8, 12
B8 – –
I/O General-purpose input/output 164
EPWM10B 1 O Enhanced PWM10 output B
GPIO165 0, 4, 8, 12
C5 – –
I/O General-purpose input/output 165
EPWM11A 1 O Enhanced PWM11 output A
GPIO166 0, 4, 8, 12
D5 – –
I/O General-purpose input/output 166
EPWM11B 1 O Enhanced PWM11 output B
GPIO167 0, 4, 8, 12
C4 – –
I/O General-purpose input/output 167
EPWM12A 1 O Enhanced PWM12 output A
GPIO168 0, 4, 8, 12
D4 – –
I/O General-purpose input/output 168
EPWM12B 1 O Enhanced PWM12 output B
RESET
XRS F19 124 69 I/OD
Device Reset (in) and Watchdog Reset (out). The
devices have a built-in power-on reset (POR) circuit.
During a power-on condition, this pin is driven low by the
device. An external circuit may also drive this pin to
assert a device reset. This pin is also driven low by the
MCU when a watchdog reset or NMI watchdog reset
occurs. During watchdog reset, the XRS pin is driven low
for the watchdog reset duration of 512 OSCCLK cycles.
A resistor with a value from 2.2 kΩ to 10 kΩ should be
placed between XRS and V
DDIO
. If a capacitor is placed
between XRS and V
SS
for noise filtering, it should be
100 nF or smaller. These values will allow the watchdog
to properly drive the XRS pin to V
OL
within 512 OSCCLK
cycles when the watchdog reset is asserted. The output
buffer of this pin is an open drain with an internal pullup.
CLOCKS
X1 G19 123 68 I
On-chip crystal-oscillator input. To use this oscillator, a
quartz crystal must be connected across X1 and X2. If
this pin is not used, it must be tied to GND.
This pin can also be used to feed a single-ended 3.3-V
level clock. In this case, X2 is a No Connect (NC).
X2 J19 121 66 O
On-chip crystal-oscillator output. A quartz crystal may be
connected across X1 and X2. If X2 is not used, it must
be left unconnected.