Datasheet

191
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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Detailed DescriptionCopyright © 2014–2016, Texas Instruments Incorporated
6.8 Direct Memory Access
The CPU has its own 6-channel DMA module. The DMA module provides a hardware method of
transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing
up bandwidth for other system functions. Additionally, the DMA has the capability to orthogonally
rearrange the data as it is transferred as well as “ping-pong” data between buffers. These features are
useful for structuring data into blocks for optimal CPU processing.
The DMA module is an event-based machine, meaning it requires a peripheral or software trigger to start
a DMA transfer. Although it can be made into a periodic time-driven machine by configuring a timer as the
interrupt trigger source, there is no mechanism within the module itself to start memory transfers
periodically. The interrupt trigger source for each of the six DMA channels can be configured separately
and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfer
has either started or completed. Five of the six channels are exactly the same, while Channel 1 has the
ability to be configured at a higher priority than the others.
DMA features include:
• Six channels with independent PIE interrupts
• Peripheral interrupt trigger sources
– ADC interrupts and EVT signals
– Multichannel buffered serial port transmit and receive
– External interrupts
– CPU timers
– EPWMxSOC signals
– SPIx transmit and receive
– SDFM
– Software trigger
• Data sources and destinations:
– GSx RAM
– ADC result registers
– ePWMx
– SPI
– McBSP
– EMIF
• Word Size: 16-bit or 32-bit (SPI and McBSP limited to 16-bit)
• Throughput: four cycles/word (without arbitration)