Datasheet

187
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Detailed DescriptionCopyright © 2014–2016, Texas Instruments Incorporated
(1) These modules are on a Peripheral Frame with DMA access; however, they cannot trigger a DMA transfer.
(2) The GPIO Data Registers are unique for each CPU1 and CPU1.CLAx. When the GPIO Pin Mapping Register is configured to assign a
GPIO to a particular master, the respective GPIO Data Register will control the GPIO. See the General-Purpose Input/Output (GPIO)
chapter of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual for more details.
6.5 Bus Architecture – Peripheral Connectivity
Table 6-9 shows a broad view of the peripheral and configuration register accessibility from each bus
master. Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master
as a group (if SPI is assigned to CPU1.DMA, then McBSP is also assigned to CPU1.DMA).
Table 6-9. Bus Master Peripheral Access
PERIPHERALS
(BY BUS ACCESS TYPE)
CPU1.DMA CPU1.CLA1 CPU1
Peripheral Frame 1:
• ePWM/HRPWM
• SDFM
• eCAP
(1)
• eQEP
(1)
• CMPSS
(1)
• DAC
(1)
Y Y Y
Peripheral Frame 2:
• SPI
• McBSP
• uPP
(1)
Y Y Y
SCI Y
I
2
C Y
CAN Y
ADC Configuration Y Y
EMIF1 Y Y
EMIF2 Y Y
USB Y
Device Capability, Peripheral Reset, Peripheral CPU Select Y
GPIO Pin Mapping and Configuration Y
Analog System Control Y
uPP Message RAMs Y Y
Reset Configuration Y
Clock and PLL Configuration Y
System Configuration
(WD, NMIWD, LPM, Peripheral Clock Gating)
Y
Flash Configuration Y
CPU Timers Y
DMA and CLA Trigger Source Select Y
GPIO Data
(2)
Y Y
ADC Results Y Y Y