Datasheet

184
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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6.3.5 Memory Types
Table 6-6 provides more information about each memory type.
Table 6-6. Memory Types
MEMORY TYPE ECC-CAPABLE PARITY SECURITY
HIBERNATE
RETENTION
ACCESS
PROTECTION
M0, M1 Yes – – Yes –
D0, D1 Yes – Yes – Yes
LSx – Yes Yes – Yes
GSx – Yes – – Yes
CPU/CLA MSGRAM – Yes Yes – Yes
Boot ROM – – – N/A –
Secure ROM – – Yes N/A –
Flash Yes – Yes N/A N/A
User-configurable DCSM OTP Yes – Yes N/A N/A
6.3.5.1 Dedicated RAM (Mx and Dx RAM)
The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1
memories are small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has
access to them). D0/D1 memories are secure blocks and also have the access-protection feature (CPU
write/CPU fetch protection).
6.3.5.2 Local Shared RAM (LSx RAM)
RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are
called local shared RAMs (LSx RAMs).
All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU
write/CPU fetch) feature.
By default, these memories are dedicated to the CPU only, and the user could choose to share these
memories with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.
Table 6-7 shows the master access for the LSx RAM.
Table 6-7. Master Access for LSx RAM
(With Assumption That all Other Access Protections are Disabled)
MSEL_LSx CLAPGM_LSx
CPU ALLOWED
ACCESS
CLA ALLOWED
ACCESS
COMMENT
00 X All –
LSx memory is configured
as CPU dedicated RAM.
01 0 All
Data Read
Data Write
LSx memory is shared
between CPU and CLA1.
01 1
Emulation Read
Emulation Write
Fetch Only
LSx memory is CLA1
program memory.