Datasheet

I1
21 3
5
4
7
6
9
Q1 I2 I3 I4 I5 I6 I7 I8 I9Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9
8
CLK
START
ENABLE
DATA[n:0]
WAIT
11
10
CLK
START
ENABLE
DATA[n:0]
Data2Data1 Data3 Data4
2
WAIT
Data5 Data6
1
Data7 Data8 Data9
3
5
4
7
6
9
8
174
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Figure 5-79. uPP Single Data Rate (SDR) Receive Timing
Figure 5-80. uPP Double Data Rate (DDR) Receive Timing