Datasheet

173
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.10.7.1 uPP Electrical Data and Timing
Table 5-93 shows the uPP timing requirements. Table 5-94 shows the uPP switching characteristics.
Figure 5-79 through Figure 5-82 show the uPP timing diagrams.
Table 5-93. uPP Timing Requirements
NO. MIN MAX UNIT
1 t
c(CLK)
Cycle time, CLK
SDR mode 20
ns
DDR mode 40
2 t
w(CLKH)
Pulse width, CLK high
SDR mode 8
ns
DDR mode 18
3 t
w(CLKL)
Pulse width, CLK low
SDR mode 8
ns
DDR mode 18
4 t
su(STV-CLKH)
Setup time, START valid before CLK high 4 ns
5 t
h(CLKH-STV)
Hold time, START valid after CLK high 0.8 ns
6 t
su(ENV-CLKH)
Setup time, ENABLE valid before CLK high 4 ns
7 t
h(CLKH-ENV)
Hold time, ENABLE valid after CLK high 0.8 ns
8 t
su(DV-CLKH)
Setup time, DATA valid before CLK high 4 ns
9 t
h(CLKH-DV)
Hold time, DATA valid after CLK high 0.8 ns
10 t
su(DV-CLKL)
Setup time, DATA valid before CLK low 4 ns
11 t
h(CLKL-DV)
Hold time, DATA valid after CLK low 0.8 ns
19 t
su(WTV-CLKH)
Setup time, WAIT valid before CLK high SDR mode 20 ns
20 t
h(CLKH-WTV)
Hold time, WAIT valid after CLK high SDR mode 0 ns
21 t
su(WTV-CLKL)
Setup time, WAIT valid before CLK low DDR mode 20 ns
22 t
h(CLKL-WTV)
Hold time, WAIT valid after CLK low DDR mode 0 ns
Table 5-94. uPP Switching Characteristics
over recommended operating conditions (unless otherwise noted)
NO. PARAMETER MIN MAX UNIT
12 t
c(CLK)
Cycle time, CLK
SDR mode 20
ns
DDR mode 40
13 t
w(CLKH)
Pulse width, CLK high
SDR mode 8
ns
DDR mode 18
14 t
w(CLKL)
Pulse width, CLK low
SDR mode 8
ns
DDR mode 18
15 t
d(CLKH-STV)
Delay time, START valid after CLK high 3 12 ns
16 t
d(CLKH-ENV)
Delay time, ENABLE valid after CLK high 3 12 ns
17 t
d(CLKH-DV)
Delay time, DATA valid after CLK high 3 12 ns
18 t
d(CLKL-DV)
Delay time, DATA valid after CLK low 3 12 ns