Datasheet

Arbit
Internal
DMA
Arbi
t
I-FIFO
Arbi
Q-FIFO
Data Interleaving
(TX/RX)
64 Bit
MEM WR I/F
64 Bit
MEM RD I/F
Transmit Timing
and Control
CLKDIVIDER
CPU1.SYSCLK
Receive Timing
and Control
Interrupt/Trigger
Configuration
I/F
G
P
I
O
M
U
X
and
I/O
C
O
N
T
R
O
L
ENABLE OUT
START OUT
WAIT IN
ENABLE IN
START IN
WAIT OUT
ENABLE/GPIOx
START/GPIOx
WAIT/GPIOx
CLK OUT
CLK IN
CLK/GPIOx
DATA OUT
DATA IN
DATA[7:0]/GPIOx
uPP
Control Mux
MMR
172
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Specifications Copyright © 2014–2016, Texas Instruments Incorporated
The uPP interface supports the following:
• Mainstream high-speed data converters with parallel conversion interface.
• Mainstream high-speed streaming interface with frame START indication.
• Mainstream high-speed streaming interface with data ENABLE indication.
• Mainstream high-speed streaming interface with synchronization WAIT signal.
• SDR (single-data-rate) or DDR (double-data-rate, interleaved) interface.
• Multiplexing of interleaved data in SDR transmit case.
• Demultiplexing and multiplexing of interleaved data in DDR case.
• I/O interface clock frequency up to 50 MHz for SDR, and 25 MHz for DDR.
• Single-channel 8-bit input receive or output transmit mode.
• Max throughput is 50MB/s for pure read or pure write.
• Available as a DSP to FPGA general-purpose streaming interface.
Figure 5-78 shows the uPP functional block diagram.
Figure 5-78. uPP Functional Block Diagram