Datasheet

Packet
Encode/Decode
Endpoint Control
EP0 –31
Control
Transmit
Receive
Combine
Endpoints
Host
Transaction
Scheduler
Packet Encode
Packet Decode
CRC Gen/Check
FIFO RAM
Controller
Cycle Control
Rx
Buff
Rx
Buff
Tx
Buff
Tx
Buff
CPU Interface
Interrupt
Control
EP Reg.
Decoder
Common
Regs
Cycle
Control
FIFO
Decoder
Interrupts
CPU Bus
UTM
Synchronization
Data Sync
HNP/SRP
Timers
USB FS/LS
PHY
USB PHY
USB DataLines
D+ andD-
169
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.10.6 Universal Serial Bus (USB) Controller
The USB controller operates as a full-speed or low-speed function controller during point-to-point
communications with USB host or device functions.
The USB module has the following features:
• USB 2.0 full-speed (12 Mbps) and low-speed (1.5 Mbps) operation
• Integrated PHY
• Three transfer types: control, interrupt, and bulk
• 32 endpoints
– One dedicated control IN endpoint and one dedicated control OUT endpoint
– 15 configurable IN endpoints and 15 configurable OUT endpoints
• 4KB of dedicated endpoint memory
Figure 5-76 shows the USB block diagram.
Figure 5-76. USB Block Diagram
NOTE
The accuracy of the on-chip zero-pin oscillator (Table 5-18, Internal Oscillator Electrical
Characteristics) will not meet the accuracy requirements of the USB protocol. An external
clock source must be used for applications using USB. For applications using the USB boot
mode, see Section 6.9 (Boot ROM and Peripheral Booting) for clock frequency requirements.