Datasheet

22
SPISIMO
SPISOMI
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
SPISIMO Data
Must Be Valid
SPISOMI Data Is Valid
21
25
18
17
SPISTE
26
Data ValidData Valid
14
13
12
168
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.10.5.1.8 High-Speed Slave Mode External Timings Where Clock Phase = 1
Table 5-90 and Figure 5-75 show the high-speed SPI slave mode external timings where the clock
phase = 1.
Table 5-90. High-Speed SPI Slave Mode External Timings Where Clock Phase = 1
NO. MIN MAX UNIT
12 t
c(SPC)S
Cycle time, SPICLK 8t
c(SYSCLK)
ns
13
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0) 4t
c(SYSCLK)
– 1
ns
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1) 4t
c(SYSCLK)
– 1
14
t
w(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0) 4t
c(SYSCLK)
– 1
ns
t
w(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1) 4t
c(SYSCLK)
– 1
17
t
d(SPCL-SOMI)S
Delay time, SPICLK low to SPISOMI (clock polarity = 0) 9
ns
t
d(SPCH-SOMI)S
Delay time, SPICLK high to SPISOMI (clock polarity = 1) 9
18
t
v(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 0)
0
ns
t
v(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 1)
0
21
t
su(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0) 5
ns
t
su(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity = 1) 5
22
t
h(SPCH-SIMO)S
Hold time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
5
ns
t
h(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
5
25
t
su(STE-SPCH)S
Setup time, SPISTE valid before SPICLK high (clock polarity = 0) 2t
c(SYSCLK)
ns
t
su(STE-SPCL)S
Setup time, SPISTE valid before SPICLK low (clock polarity = 1) 2t
c(SYSCLK)
26
t
h(STE-SPCL)S
Hold time, SPISTE invalid after SPICLK low (clock polarity = 0) 2t
c(SYSCLK)
ns
t
h(STE-SPCH)S
Hold time, SPISTE invalid after SPICLK high (clock polarity = 1) 2t
c(SYSCLK)
Figure 5-75. High-Speed SPI Slave Mode External Timing (Clock Phase = 1)