Datasheet

161
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.10.5.1.5 High-Speed Master Mode External Timings Where Clock Phase = 0
Table 5-85 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is even or
SPIBRR = 0 or 2.
Table 5-86 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is odd and
SPIBRR > 3.
Figure 5-72 shows the high-speed SPI master mode external timing where the clock phase = 0.
Table 5-85. High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Even or
SPIBRR = 0 or 2
NO. MIN MAX UNIT
1 t
c(SPC)M
Cycle time, SPICLK 4t
c(LSPCLK)
128t
c(LSPCLK)
ns
2
t
w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5t
c(SPC)M
– 1 0.5t
c(SPC)M
+ 1
ns
t
w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5t
c(SPC)M
– 1 0.5t
c(SPC)M
+ 1
3
t
w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t
c(SPC)M
– 1 0.5
tc(SPC)M
+ 1
ns
t
w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5
tc(SPC)M
– 1 0.5t
c(SPC)M
+ 1
4
t
d(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO valid
(clock polarity = 0)
1
ns
t
d(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO valid
(clock polarity = 1)
1
5
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK
low (clock polarity = 0)
0.5t
c(SPC)M
– 1
ns
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK
high (clock polarity = 1)
0.5t
c(SPC)M
– 1
8
t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
1
ns
t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
1
9
t
h(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK
low (clock polarity = 0)
5
ns
t
h(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK
high (clock polarity = 1)
5
23
t
d(STE-SPCH)M
Delay time, SPISTE low to SPICLK high (clock
polarity = 0)
0.5t
c(SPC)
– 1
ns
t
d(STE-SPCL)M
Delay time, SPISTE low to SPICLK low (clock
polarity = 1)
0.5t
c(SPC)
– 1
24
t
d(SPCL-STE)M
Delay time, SPICLK low to SPISTE invalid
(clock polarity = 0)
0.5t
c(SPC)
– 1
ns
t
d(SPCH-STE)M
Delay time, SPICLK high to SPISTE invalid
(clock polarity = 1)
0.5t
c(SPC)
– 1