Datasheet

156
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.10.5.1.2 Master Mode External Timings Where Clock Phase = 1
Table 5-81 shows the SPI master mode external timings where (SPIBRR + 1) is even or SPIBRR = 0 or 2.
Table 5-82 shows the SPI master mode external timings where (SPIBRR + 1) is odd or SPIBRR > 3.
Figure 5-69 shows the SPI master mode external timing where the clock phase = 1.
Table 5-81. SPI Master Mode External Timings Where (SPIBRR + 1) is Even or SPIBRR = 0 or 2
NO. MIN MAX UNIT
1 t
c(SPC)M
Cycle time, SPICLK 4t
c(LSPCLK)
128t
c(LSPCLK)
ns
2
t
w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 0)
0.5t
c(SPC)M
– 1 0.5t
c(SPC)M
+ 1
ns
t
w(SPCL))M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5t
c(SPC)M
– 1 0.5t
c(SPC)M
+ 1
3
t
w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t
c(SPC)M
– 1 0.5t
c(SPC)M
+ 1
ns
t
w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5t
c(SPC)M
– 1 0.5t
c(SPC)M
+ 1
6
t
d(SIMO-SPCH)M
Delay time, SPISIMO data valid to SPICLK
high (clock polarity = 0)
0.5t
c(SPC)M
– 3
ns
t
d(SIMO-SPCL)M
Delay time, SPISIMO data valid to SPICLK low
(clock polarity = 1)
0.5t
c(SPC)M
– 3
7
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK
high (clock polarity = 0)
0.5t
c(SPC)M
– 3
ns
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK
low (clock polarity = 1)
0.5t
c(SPC)M
– 3
10
t
su(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 0)
20
ns
t
su(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 1)
20
11
t
h(SPCH-SOMI)M
Hold time, SPISOMI data valid after SPICLK
high (clock polarity = 0)
0
ns
t
h(SPCL-SOMI)M
Hold time, SPISOMI data valid after SPICLK
low (clock polarity = 1)
0
23
t
d(STE-SPCH)M
Delay time, SPISTE low to SPICLK high (clock
polarity = 0)
0.5t
c(SPC)
– 3
ns
t
d(STE-SPCL)M
Delay time, SPISTE low to SPICLK low (clock
polarity = 1)
0.5t
c(SPC)
– 3
24
t
d(SPCL-STE)M
Delay time, SPICLK low to SPISTE invalid
(clock polarity = 0)
0.5t
c(SPC)
– 3
ns
t
d(SPCH-STE)M
Delay time, SPICLK high to SPISTE invalid
(clock polarity = 1)
0.5t
c(SPC)
– 3