Datasheet

9
4
SPISOMI
SPISIMO
SPICLK
(clock polarity = 1)
SPICLK
(clock polarity = 0)
Master In Data
Must Be Valid
8
Master Out Data Is Valid
3
2
1
SPISTE
(A)
5
23
24
155
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and
non-FIFO modes.
Figure 5-68. SPI Master Mode External Timing (Clock Phase = 0)