Datasheet

WUT
Frame Format and Mode
Even/Odd Enable
Parity
SCI RX Interrupt select logic
BRKDT
RXRDY
SCIRXST.6
SCICTL1.3
SCICTL2.1
RX/BK INT ENA
SCIRXD
TXENA
SCI TX Interrupt select logic
TX EMPTY
TXRDY
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCICCR.6 SCICCR.5
SCITXBUF.7−0
SCIHBAUD. 15 − 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 − 0
Transmitter-Data
Buffer Register
8
SCICTL2.6
SCICTL2.7
Baud Rate
LSbyte
Register
SCIRXST.1
LSPCLK
RXSHF
Register
TXSHF
Register
SCIRXST.5
1
8
TX FIFO registers
TX FIFO Interrupt
TX Interrupt
Logic
TXINT
SCIFFTX.14
SCICTL1.0
8
RX Interrupt
Logic
RXINT
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
PE
OE
FE
RX Error
To CPU
To CPU
SCICTL1.1
SCIFFENA
Auto baud detect logic
SCIRXST.4 – 2
TX FIFO _0
TX FIFO _1
−−−−−
TX FIFO _15
Receive Data
Buffer register
SCIRXBUF.7−0
RX FIFO registers
RX FIFO Interrupt
RX FIFO _15
SCIRXBUF.7−0
−−−−−
RX FIFO_1
RX FIFO _0
8
148
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Figure 5-66. SCI Block Diagram