Datasheet

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
DR
M54
M58
M56
M53
M55
M59
M57
LSB
MSB
M60
M61
146
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
For CLKSTP = 11b and CLKXP = 1, Table 5-77 shows the timing requirements, Table 5-78 shows the
switching characteristics, and Figure 5-65 shows the timing diagram.
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 5-77. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
(1)
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M58 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 30 8P – 10 ns
M59 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 1 8P – 10 ns
M60 t
su(FXL-CKXL)
Setup time, FSX low before CLKX low 16P + 10 ns
M61 t
c(CKX)
Cycle time, CLKX 2P
(2)
16P ns
(1) 2P = 1/CLKG
(2) C = CLKX low pulse width = P
D = CLKX high pulse width = P
Table 5-78. McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating
Conditions (Unless Otherwise Noted) (CLKSTP = 11b, CLKXP = 1)
(1)
NO. PARAMETER
MASTER
(2)
SLAVE
UNIT
MIN MAX MIN MAX
M53 t
h(CKXH-FXL)
Hold time, FSX low after CLKX high P ns
M54 t
d(FXL-CKXL)
Delay time, FSX low to CLKX low 2P
(1)
ns
M55 t
d(CLKXH-DXV)
Delay time, CLKX high to DX valid –2 0 3P + 6 5P + 20 ns
M56 t
dis(CKXH-DXHZ)
Disable time, DX high impedance following last
data bit from CLKX high
P + 6 7P + 6 ns
M57 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
Figure 5-65. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1