Datasheet

Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
Bit 0 Bit(n-1) (n-2) (n-3) (n-4)
CLKX
FSX
DX
M30
M31
DR
M28
M24
M29
M25
LSB
MSB
M32
M33
143
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www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.10.3.1.2 McBSP as SPI Master or Slave Timing
For CLKSTP = 10b and CLKXP = 0, Table 5-71 shows the timing requirements, Table 5-72 shows the
switching characteristics, and Figure 5-62 shows the timing diagram.
(1) For all SPI slave modes, CLKX has to be a minimum of 8 CLKG cycles. Furthermore, CLKG should be LSPCLK/2 by setting CLKSM =
CLKGDV = 1.
(2) 2P = 1/CLKG
Table 5-71. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
(1)
NO.
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M30 t
su(DRV-CKXL)
Setup time, DR valid before CLKX low 30 8P – 10 ns
M31 t
h(CKXL-DRV)
Hold time, DR valid after CLKX low 1 8P – 10 ns
M32 t
su(BFXL-CKXH)
Setup time, FSX low before CLKX high 8P + 10 ns
M33 t
c(CKX)
Cycle time, CLKX 2P
(2)
16P ns
(1) 2P = 1/CLKG
Table 5-72. McBSP as SPI Master or Slave Switching Characteristics Over Recommended Operating
Conditions (Unless Otherwise Noted) (CLKSTP = 10b, CLKXP = 0)
NO. PARAMETER
MASTER SLAVE
UNIT
MIN MAX MIN MAX
M24 t
h(CKXL-FXL)
Hold time, FSX low after CLKX low 2P
(1)
ns
M25 t
d(FXL-CKXH)
Delay time, FSX low to CLKX high P ns
M28 t
dis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
6 6P + 6 ns
M29 t
d(FXL-DXV)
Delay time, FSX low to DX valid 6 4P + 6 ns
Figure 5-62. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0