Datasheet

140
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: TMS320F28379S TMS320F28377S TMS320F28376S TMS320F28375S TMS320F28374S
Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.10.3.1 McBSP Electrical Data and Timing
5.10.3.1.1 McBSP Transmit and Receive Timing
Table 5-69 shows the McBSP timing requirements. Table 5-70 shows the McBSP switching
characteristics. Figure 5-60 and Figure 5-61 show the McBSP timing diagrams.
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) 2P = 1/CLKG in ns. CLKG is the output of sample rate generator mux. CLKG = CLKSRG / (1 + CLKGDV). CLKSRG can be LSPCLK,
CLKX, CLKR as source. CLKSRG ≤ (SYSCLK/2).
Table 5-69. McBSP Timing Requirements
(1) (2)
NO. MIN MAX UNIT
McBSP module clock (CLKG, CLKX, CLKR) range
1 kHz
25 MHz
McBSP module cycle time (CLKG, CLKX, CLKR) range
40 ns
1 ms
M11 t
c(CKRX)
Cycle time, CLKR/X CLKR/X ext 2P ns
M12 t
w(CKRX)
Pulse duration, CLKR/X high or CLKR/X low CLKR/X ext P – 7 ns
M13 t
r(CKRX)
Rise time, CLKR/X CLKR/X ext 7 ns
M14 t
f(CKRX)
Fall time, CLKR/X CLKR/X ext 7 ns
M15 t
su(FRH-CKRL)
Setup time, external FSR high before CLKR low
CLKR int 18
ns
CLKR ext 2
M16 t
h(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int 0
ns
CLKR ext 6
M17 t
su(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int 18
ns
CLKR ext 5
M18 t
h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int 0
ns
CLKR ext 3
M19 t
su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int 18
ns
CLKX ext 2
M20 t
h(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int 0
ns
CLKX ext 6