Datasheet

137
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
www.ti.com SPRS881C –AUGUST 2014–REVISED MAY 2016
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SpecificationsCopyright © 2014–2016, Texas Instruments Incorporated
5.10.2.1 I
2
C Electrical Data and Timing
Table 5-67 shows the I
2
C timing requirements. Table 5-68 shows the I
2
C switching characteristics.
Table 5-67. I
2
C Timing Requirements
MIN MAX UNIT
t
h(SDA-SCL)START
Hold time, START condition, SCL fall delay
after SDA fall
0.6 µs
t
su(SCL-SDA)START
Setup time, Repeated START, SCL rise before
SDA fall delay
0.6 µs
t
h(SCL-DAT)
Hold time, data after SCL fall 0 µs
t
su(DAT-SCL)
Setup time, data before SCL rise 100 ns
t
r(SDA)
Rise time, SDA Input tolerance 20 300 ns
t
r(SCL)
Rise time, SCL Input tolerance 20 300 ns
t
f(SDA)
Fall time, SDA Input tolerance 11.4 300 ns
t
f(SCL)
Fall time, SCL Input tolerance 11.4 300 ns
t
su(SCL-SDA)STOP
Setup time, STOP condition, SCL rise before
SDA rise delay
0.6 µs
Table 5-68. I
2
C Switching Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
f
SCL
SCL clock frequency 0 400 kHz
t
w(SCLL)
Pulse duration, SCL clock low 1.3 µs
t
w(SCLH)
Pulse duration, SCL clock high 0.6 µs
t
w(SP)
Pulse duration of spikes that will be
suppressed by the input filter
0 50 ns
t
BUF
Bus free time between STOP and START
conditions
1.3 µs
t
v(SCL-DAT)
Valid time, data after SCL fall 0.9 µs
t
v(SCL-ACK)
Valid time, Acknowledge after SCL fall 0.9 µs
V
IL
Valid low-level input voltage –0.3 0.3 * V
DDIO
V
V
IH
Valid high-level input voltage 0.7 * V
DDIO
V
DDIO
+ 0.3 V
V
OL
Low-level output voltage Sinking 3 mA 0 0.4 V
I
I
Input current on pins 0.1 V
bus
< V
i
< 0.9 V
bus
–10 10 µA