Datasheet

t
w(SDCH)M1
t
c(SDC)M1
t
h(SDCL-SDD)M1
t
h(SDCH-SDD)M1
t
su(SDDV-SDCL)M1
t
su(SDDV-SDCH)M1
SDx_Cy
SDx_Dy
Mode 1
Mode 0
t
w(SDCH)M0
t
c(SDC)M0
t
h(SDCH-SDD)M0
t
su(SDDV-SDCH)M0
SDx_Cy
SDx_Dy
132
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.9.5.1 SDFM Electrical Data and Timing
Table 5-66 shows the SDFM timing requirements. Figure 5-54 through Figure 5-57 show the SDFM timing
diagrams.
Table 5-66. SDFM Timing Requirements
MIN MAX UNIT
Mode 0
t
c(SDC)M0
Cycle time, SDx_Cy 40 256 * SYSCLK period ns
t
w(SDCH)M0
Pulse duration, SDx_Cy high 10 t
c(SDC)M0
– 10 ns
t
su(SDDV-SDCH)M0
Setup time, SDx_Dy valid before SDx_Cy goes
high
5 ns
t
h(SDCH-SDD)M0
Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Mode 1
t
c(SDC)M1
Cycle time, SDx_Cy 80 256 * SYSCLK period ns
t
w(SDCH)M1
Pulse duration, SDx_Cy high 10 t
c(SDC)M1
– 10 ns
t
su(SDDV-SDCL)M1
Setup time, SDx_Dy valid before SDx_Cy goes low 5 ns
t
su(SDDV-SDCH)M1
Setup time, SDx_Dy valid before SDx_Cy goes
high
5 ns
t
h(SDCL-SDD)M1
Hold time, SDx_Dy wait after SDx_Cy goes low 5 ns
t
h(SDCH-SDD)M1
Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Mode 2
t
c(SDD)M2
Cycle time, SDx_Dy 8 * t
c(SYSCLK)
20 * t
c(SYSCLK)
ns
t
w(SDDH)M2
Pulse duration, SDx_Dy high 10 ns
Mode 3
t
c(SDC)M3
Cycle time, SDx_Cy 40 256 * SYSCLK period ns
t
w(SDCH)M3
Pulse duration, SDx_Cy high 10 t
c(SDC)M3
– 5 ns
t
su(SDDV-SDCH)M3
Setup time, SDx_Dy valid before SDx_Cy goes
high
5 ns
t
h(SDCH-SDD)M3
Hold time, SDx_Dy wait after SDx_Cy goes high 5 ns
Figure 5-54. SDFM Timing Diagram – Mode 0
Figure 5-55. SDFM Timing Diagram – Mode 1