Datasheet

TSCTR
(counter−32 bit)
RST
CAP1
(APRD active)
LD
CAP2
(ACMP active)
LD
CAP3
(APRD shadow)
LD
CAP4
(ACMP shadow)
LD
Continuous /
Oneshot
Capture Control
LD1
LD2
LD3
LD4
32
32
PRD [0−31]
CMP [0−31]
CTR [0−31]
eCAPx
Interrupt
Trigger
and
Flag
control
to PIE
CTR=CMP
32
32
32
32
32
ACMP
shadow
Event
Prescale
CTRPHS
(phase register−32 bit)
SYNCOut
SYNCIn
Event
qualifier
Polarity
select
Polarity
select
Polarity
select
Polarity
select
CTR=PRD
CTR_OVF
4
PWM
compare
logic
CTR [0−31]
PRD [0−31]
CMP [0−31]
CTR=CMP
CTR=PRD
CTR_OVF
OVF
APWM mode
Delta−mode
SYNC
4
Capture events
CEVT[1:4]
APRD
shadow
32
32
MODE SELECT
Copyright © 2016, Texas Instruments Incorporated
118
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
Figure 5-46. eCAP Block Diagram
The eCAP module is clocked by PERx.SYSCLK.
The clock enable bits (ECAP1–ECAP6) in the PCLKCR3 register turn off the eCAP module individually
(for low-power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock
is off.