Datasheet
114
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.8.3.1 Buffered DAC Electrical Data and Timing
Table 5-56 shows the buffered DAC electrical characteristics. Figure 5-43 shows the buffered DAC offset.
Figure 5-44 shows the buffered DAC gain. Figure 5-45 shows the buffered DAC linearity.
(1) Typical values are measured with V
REFHI
= 3.3 V and V
REFLO
= 0 V unless otherwise noted. Minimum and Maximum values are tested
or characterized with V
REFHI
= 2.5 V and V
REFLO
= 0 V.
(2) Gain error is calculated for linear output range.
(3) The DAC output is monotonic.
(4) This is the linear output range of the DAC. The DAC can generate voltages outside this range, but the output voltage will not be linear
due to the buffer.
(5) For best PSRR performance, VDAC or V
REFHI
should be less than V
DDA
.
(6) Per active Buffered DAC module.
(7) V
REFHI
= 3.2 V, V
DDA
= 3.3 V DC + 100 mV Sine.
Table 5-56. Buffered DAC Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time (DACOUTEN to DAC
output valid)
10 µs
Trimmed offset error Midpoint –10 10 mV
Gain error
(2)
–2.5 2.5 % of FSR
DNL
(3)
Endpoint corrected > –1 1 LSB
INL Endpoint corrected –5 5 LSB
DACOUTx settling time
Settling to 2 LSBs after 0.3V-to-3V
transition
2 µs
Resolution 12 bits
Voltage output range
(4)
0.3 V
DDA
– 0.3 V
Capacitive load Output drive capability 100 pF
Resistive load Output drive capability 5 kΩ
R
PD
50 kΩ
Reference voltage
(5)
VDAC or V
REFHI
2.4 2.5 or 3.0 V
DDA
V
Reference load
(6)
VDAC or V
REFHI
170 kΩ
Output noise
Integrated noise from 100 Hz to 100 kHz 500 µVrms
Noise density at 10 kHz 711 nVrms/√Hz
Glitch energy 1.5 V-ns
PSRR
(7)
DC up to 1 kHz 70
dB
100 kHz 30
SNR 1020 Hz 67 dB
THD 1020 Hz –63 dB
SFDR
1020 Hz, including harmonics and spurs 66
dBc
1020 Hz, including only spurs 104
NOTE
The VDAC pin must be kept below V
DDA
+ 0.3 V to ensure proper functional operation. If the
VDAC pin exceeds this level, a blocking circuit may activate, and the internal value of VDAC
may float to 0 V internally, giving improper DAC output.