Datasheet

CTRIPx = 0
0
CMPINxN or
DACxVAL
CTRIPx = 1
Hysteresis
COMPINxP
Voltage
CTRIPx
Logic Level
CTRIPx = 0
0
CMPINxN or
DACxVAL
CTRIPx = 1
Input Referred Offset
COMPINxP
Voltage
CTRIPx
Logic Level
110
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
5.8.2.1 CMPSS Electrical Data and Timing
Table 5-54 shows the comparator electrical characteristics. Figure 5-37 shows the CMPSS comparator
input referred offset. Figure 5-38 shows the CMPSS comparator hysteresis.
(1) Hysteresis will scale with the CMPSS reference voltage.
Table 5-54. Comparator Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power-up time (from COMPCTL[COMPDACE] to
comparator ready)
10 µs
Comparator input (CMPINxx) range 0 V
DDA
V
Input referred offset error –20 20 mV
Hysteresis
(1)
1x 12
CMPSS
DAC LSB
2x 24
3x 36
4x 48
Response time (delay from CMPINx input change
to output on ePWM X-BAR or Output X-BAR)
Step response 21 60
nsRamp response (1.65 V/µs) 26
Ramp response (8.25 mV/µs) 30
NOTE
The CMPSS inputs must be kept below V
DDA
+ 0.3 V to ensure proper functional operation. If
a CMPSS input exceeds this level, an internal blocking circuit will isolate the internal
comparator from the external pin until the external pin voltage returns below V
DDA
+ 0.3 V.
During this time, the internal comparator input will be floating and can decay below V
DDA
within approximately 0.5 µs. After this time, the comparator could begin to output an incorrect
result depending on the value of the other comparator input.
Figure 5-37. CMPSS Comparator Input Referred Offset
Figure 5-38. CMPSS Comparator Hysteresis