Datasheet

ADC
R
on
Switch
ADCINxN
C
h
C
p
ADCINxP
AC
R
s
R
on
Switch
R
s
C
p
VSSA
ADC
R
on
Switch
VREFLO
C
h
C
p
ADCINx
AC
R
s
102
TMS320F28379S , TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016 www.ti.com
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Specifications Copyright © 2014–2016, Texas Instruments Incorporated
(1) For an explanation of the input qualifier parameters, see Table 5-26.
Table 5-47. ADCEXTSOC Timing Requirements
(1)
MIN MAX UNIT
t
w(INT)
Pulse duration, INT input low/high
Synchronous 2t
c(SYSCLK)
cycles
With qualifier t
w(IQSW)
+ t
w(SP)
+ 1t
c(SYSCLK)
cycles
5.8.1.1.1 ADC Input Models
NOTE
ADC channels ADCINA0, ADCINA1, and ADCINB1 have a 50-kΩ pulldown resistor to V
SSA
.
For single-ended operation, the ADC input characteristics are given by Table 5-48 and Figure 5-31.
Table 5-48. Single-Ended Input Model Parameters
DESCRIPTION VALUE (12-BIT MODE)
C
p
Parasitic input capacitance See Table 5-50
R
on
Sampling switch resistance 425 Ω
C
h
Sampling capacitor 14.5 pF
R
s
Nominal source impedance 50 Ω
Figure 5-31. Single-Ended Input Model
For differential operation, the ADC input characteristics are given by Table 5-49 and Figure 5-32.
Table 5-49. Differential Input Model Parameters
DESCRIPTION VALUE (16-BIT MODE)
C
p
Parasitic input capacitance See Table 5-50
R
on
Sampling switch resistance 700 Ω
C
h
Sampling capacitor 16.5 pF
R
s
Nominal source impedance 50 Ω
Figure 5-32. Differential Input Model