Datasheet
W
V
U
T
R
P
N
M
L
K
10987654321
654321
V
SS
V
SSA
V
SSA
V
SSA
V
SSA
V
SSA
V
DDA
V
DDA
V
REFHIB
V
REFLOB
V
REFHID
V
REFLOD
V
REFHIA
V
REFHIC
V
REFLOA
V
REFLOC
W
V
U
T
GPIO129GPIO125
GPIO23
GPIO24GPIO25GPIO26
GPIO27 GPIO108GPIO107GPIO106
GPIO111GPIO112GPIO110
GPIO109 GPIO114
GPIO113
GPIO122
ADCIND4ADCIND2ADCIND0ADCIN14
ADCIN15
ADCINC5
ADCINC3
ADCINC2
ADCINA5
ADCINA3
ADCINA1
ADCINA0 ADCINA2 ADCINA4
ADCINC4
ADCIND1
ADCIND3
ADCINB4ADCINB2ADCINB0
ADCINB1
ADCINB3
ADCINB5
ADCIND5 GPIO123
GPIO124
GPIO126
GPIO127
GPIO128
GPIO130
GPIO131
GPIO116
R
P
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DD
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
1098
M
L
K
N
M
L
K
10987
10
TMS320F28379S
,
TMS320F28377S
TMS320F28376S, TMS320F28375S, TMS320F28374S
SPRS881C –AUGUST 2014–REVISED MAY 2016
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Terminal Configuration and Functions Copyright © 2014–2016, Texas Instruments Incorporated
4 Terminal Configuration and Functions
4.1 Pin Diagrams
Figure 4-1 to Figure 4-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid
Array. Each figure shows a quadrant of the terminal assignments. Figure 4-5 shows the pin assignments
on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack. Figure 4-6 shows the pin
assignments on the 100-pin PZP PowerPAD Thermally Enhanced Thin Quad Flatpack.
A. Only the GPIO function is shown on GPIO terminals. See Table 4-1 for the complete, muxed signal name.
Figure 4-1. 337-Ball ZWT New Fine Pitch Ball Grid Array (Bottom View) – [Quadrant A]