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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TMS320F28379S

TMS320F28377S

TMS320F28376S, TMS320F28375S, TMS320F28374S

SPRS881C –AUGUST 2014–REVISED MAY 2016

TMS320F2837xS Delfino™ Microcontrollers

1 Device Overview

1.1 Features

• TMS320C28x 32-Bit CPU

– 200 MHz

– IEEE 754 Single-Precision Floating-Point Unit

(FPU)

– Trigonometric Math Unit (TMU)

– Viterbi/Complex Math Unit (VCU-II)

• Programmable Control Law Accelerator (CLA)

– 200 MHz

– IEEE 754 Single-Precision Floating-Point

Instructions

– Executes Code Independently of Main CPU

• On-Chip Memory

– 512KB (256KW) or 1MB (512KW) of Flash

(ECC-Protected)

– 132KB (66KW) or 164KB (82KW) of RAM

(ECC-Protected or Parity-Protected)

– Dual-Zone Security Supporting Third-Party

Development

• Clock and System Control

– Two Internal Zero-Pin 10-MHz Oscillators

– On-Chip Crystal Oscillator

– Windowed Watchdog Timer Module

– Missing Clock Detection Circuitry

• 1.2-V Core, 3.3-V I/O Design

• System Peripherals

– Two External Memory Interfaces (EMIFs) With

ASRAM and SDRAM Support

– 6-Channel Direct Memory Access (DMA)

Controller

– Up to 169 Individually Programmable,

Multiplexed General-Purpose Input/Output

(GPIO) Pins With Input Filtering

– Expanded Peripheral Interrupt Controller (ePIE)

– Multiple Low-Power Mode (LPM) Support With

External Wakeup

• Communications Peripherals

– USB 2.0 (MAC + PHY)

– Support for 12-Pin 3.3 V-Compatible Universal

Parallel Port (uPP) Interface

– Two Controller Area Network (CAN) Modules

(Pin-Bootable)

– Three High-Speed (up to 50-MHz) SPI Ports

(Pin-Bootable)

– Two Multichannel Buffered Serial Ports

(McBSPs)

– Four Serial Communications Interfaces

(SCI/UART) (Pin-Bootable)

– Two I

C Interfaces (Pin-Bootable)

• Analog Subsystem

– Up to Four Analog-to-Digital Converters (ADCs)

• 16-Bit Mode

– 1.1 MSPS Each (up to 4.4-MSPS System

Throughput)

– Differential Inputs

– Up to 12 External Channels

• 12-Bit Mode

– 3.5 MSPS Each (up to 14-MSPS System

Throughput)

– Single-Ended Inputs

– Up to 24 External Channels

• Single Sample-and-Hold (S/H) on Each ADC

• Hardware-Integrated Post-Processing of

ADC Conversions

– Saturating Offset Calibration

– Error From Setpoint Calculation

– High, Low, and Zero-Crossing Compare,

With Interrupt Capability

– Trigger-to-Sample Delay Capture

– Eight Windowed Comparators With 12-Bit

Digital-to-Analog Converter (DAC) References

– Three 12-Bit Buffered DAC Outputs

• Enhanced Control Peripherals

– 24 PWM Channels With Enhanced Features

– 16 High-Resolution Pulse Width Modulator

(HRPWM) Channels

• High Resolution on Both A and B Channels

of 8 PWM Modules

• Dead-Band Support (on Both Standard and

High Resolution)

– Six Enhanced Capture (eCAP) Modules

– Three Enhanced Quadrature Encoder Pulse

(eQEP) Modules

– Eight Sigma-Delta Filter Module (SDFM) Input

Channels, 2 Parallel Filters per Channel

• Standard SDFM Data Filtering

• Comparator Filter for Fast Action for Out of

Range

Summary of content (244 pages)

PAGE 1
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 TMS320F2837xS Delfino™ Microcontrollers 1 Device Overview 1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 • Package Options: – Lead-Free, Green Packaging – 337-Ball New Fine Pitch Ball Grid Array (nFBGA) [ZWT Suffix] – 176-Pin PowerPAD™ Thermally Enhanced LowProfile Quad Flatpack (HLQFP) [PTP Suffix] – 100-Pin PowerPAD Thermally Enhanced Thin Quad Flatpack (HTQFP) [PZP Suffix] 1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Device Information (1) PACKAGE BODY SIZE TMS320F28379SZWT PART NUMBER nFBGA (337) 16.0 mm × 16.0 mm TMS320F28377SZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28376SZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28375SZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28374SZWT nFBGA (337) 16.0 mm × 16.0 mm TMS320F28379SPTP HLQFP (176) 24.0 mm × 24.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 1.4 www.ti.com Functional Block Diagram Figure 1-1 shows the CPU system and associated peripherals. MEMCPU1 CPU1.CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1.CLA1 128x16 MSG RAM CPU1.CLA1 C28 CPU-1 Dual Code Security Module + Emulation Code Security Logic (ECSL) CPU1 Local Shared 6x 2Kx16 LS0-LS5 RAMs Secure Memories shown in Red CPU1.D0 RAM 2Kx16 CPU1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table of Contents 1 Device Overview ......................................... 1 6.3 Memory 1.1 Features .............................................. 1 6.4 Identification........................................ 186 1.2 Applications ........................................... 2 6.5 Bus Architecture – Peripheral Connectivity ........ 187 1.3 Description ................
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from October 22, 2015 to May 6, 2016 (from B Revision (October 2015) to C Revision) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 6 Page Global: Restructured document. ...........................................................................
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 3 Device Comparison Table 3-1 lists the features of each 2837xS device. Table 3-1. Device Comparison 28379S FEATURE(1) Package Type (ZWT is an nFBGA package. PTP is an HLQFP package. PZP is an HTQFP package.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 3-1. Device Comparison (continued) 28379S FEATURE(1) Package Type (ZWT is an nFBGA package. PTP is an HLQFP package. PZP is an HTQFP package.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 3.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 4 Terminal Configuration and Functions 4.1 Pin Diagrams Figure 4-1 to Figure 4-4 show the terminal assignments on the 337-ball ZWT New Fine Pitch Ball Grid Array. Each figure shows a quadrant of the terminal assignments. Figure 4-5 shows the pin assignments on the 176-pin PTP PowerPAD Thermally Enhanced Low-Profile Quad Flatpack.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com A.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 A. www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S GPIO60 GPIO59 GPIO58 GPIO41 54 53 52 51 56 55 GPIO62 GPIO61 VDDIO 57 GPIO64 GPIO63 59 58 GPIO66 GPIO65 60 VDDIO 62 61 VREGENZ VDD 64 63 X2 VDDOSC 66 X1 VSSOSC 65 XRS 69 68 67 VDD VDDOSC 71 72 70 GPIO43 GPIO42 VDDIO 73 GPIO69 GPIO70 76 50 TCK GPIO71 VDD 77 49 TMS 78 48 TRST VDDIO 79 47 TDO GPIO72 80 46 GPIO73 81 45 TDI VDD GPIO78 VDDIO 82 44 VDDIO 83 43 FLT2 VDD 84 42
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 4.2 www.ti.com Signal Descriptions Table 4-1 describes the signals. The GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 3-1 for details.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL ZWT BALL NO. PTP PIN NO. PZP PIN NO. I/O/Z(1) DESCRIPTION I ADC-A input 1. There is a 50-kΩ internal pulldown on this pin in both an ADC input or DAC output mode which cannot be disabled.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO8 MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO14 MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO26 MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO34 MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO45 MUX POSITION 0, 4, 8, 12 EM1A5 2 GPIO46 0, 4, 8, 12 EM1A6 2 SCIRXDD 6 GPIO47 0, 4, 8, 12 EM1A7 2 SCITXDD GPIO48 ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO54 MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
PAGE 27
TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
PAGE 28
TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION GPIO76 0, 4, 8, 12 EM1D8 2 SCITXDD 6 GPIO77 0, 4, 8, 12 EM1D7 2 SCIRXDD ZWT BALL NO. C16 A15 PTP PIN NO. 143 144 PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION GPIO88 0, 2, 4, 8 EM1A15 2 EM1DQM0 3 GPIO89 ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO102 MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME GPIO117 MUX POSITION 0, 4, 8, 12 EM2SDCKE 3 GPIO118 0, 4, 8, 12 EM2CLK 3 GPIO119 0, 4, 8, 12 EM2RNW 3 GPIO120 0, 4, 8, 12 EM2WE 3 USB0PFLT GPIO121 EM2OE GPIO122 PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1.
PAGE 34
TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO. I/O/Z(1) DESCRIPTION NO CONNECT No connect. BGA ball is electrically open and not connected to the die. NC H4 – – TCK V15 81 50 I JTAG test clock with internal pullup (see Section 5.5) TDI W13 77 46 I JTAG test data input (TDI) with internal pullup.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME VDDIO VDDOSC MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO. PWR PAD PWR PAD I/O/Z(1) DESCRIPTION A1 A10 A19 E5 E6 E8 E12 E14 E15 F5 F6 F8 F12 F14 F15 G16 G17 H8 H9 H10 VSS H11 H12 Analog and digital ground. For Quad Flatpacks (QFPs), the PowerPAD on the bottom of the package must be soldered to the ground plane of the PCB.
PAGE 37
TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO. PWR PAD PWR PAD H18 122 67 H19 – – P1 34 17 P5 52 35 R5 – 36 V7 – – W1 – – I/O/Z(1) DESCRIPTION L10 L11 L12 L18 M8 M9 M10 M11 M12 M14 M15 N1 VSS N5 N6 Analog and digital ground.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-1. Signal Descriptions (continued) TERMINAL NAME MUX POSITION ZWT BALL NO. PTP PIN NO. PZP PIN NO. I/O/Z(1) DESCRIPTION SPECIAL FUNCTIONS ERRORSTS U19 92 – O Error status output. This pin has an internal pulldown. TEST PINS FLT1 W12 73 42 I/O Flash test pin 1. Reserved for TI. Must be left unconnected. FLT2 V13 74 43 I/O Flash test pin 2.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 4.4 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Connections for Unused Pins For applications that do not need to use all functions of the device, Table 4-3 lists acceptable conditioning for any unused pins. When multiple options are listed in Table 4-3, any are acceptable. Pins not listed in Table 4-3 must be connected according to Table 4-1. Table 4-3.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 4.5 www.ti.com Pin Multiplexing 4.5.1 GPIO Muxed Pins Table 4-4 shows the GPIO muxed pins. The default for each pin is the GPIO function, secondary functions can be selected by setting both the GPyGMUXn.GPIOz and GPyMUXn.GPIOz register bits. The GPyGMUXn register should be configured prior to the GPyMUXn to avoid transient pulses on GPIO's from alternate mux selections.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-4. GPIO Muxed Pins(1)(2) (continued) GPIO Mux Selection GPIO Index 0, 4, 8, 12 GPyGMUXn. GPIOz = 00b, 01b, 10b, 11b GPyMUXn.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 4-4. GPIO Muxed Pins(1)(2) (continued) GPIO Mux Selection GPIO Index 0, 4, 8, 12 GPyGMUXn. GPIOz = 00b, 01b, 10b, 11b GPyMUXn.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 4-4. GPIO Muxed Pins(1)(2) (continued) GPIO Mux Selection GPIO Index 0, 4, 8, 12 GPyGMUXn. GPIOz = 00b, 01b, 10b, 11b GPyMUXn.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 4.5.2 www.ti.com Input X-BAR The Input X-BAR is used to route any GPIO input to the ADC, eCAP, and ePWM peripherals as well as to external interrupts (XINT) (see Figure 4-7). Table 4-5 shows the input X-BAR destinations. For details on configuring the Input X-BAR, see the Crossbar (X-BAR) chapter of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 4.5.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Output X-BAR and ePWM X-BAR The Output X-BAR has eight outputs which can be selected on the GPIO mux as OUTPUTXBARx. The ePWM X-BAR has eight outputs which are connected to the TRIPx inputs of the ePWM. The sources for both the Output X-BAR and ePWM X-BAR are shown in Figure 4-8.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 4.5.4 www.ti.com USB Pin Muxing Table 4-6 shows assignment of the alternate USB function mapping. These can be configured with the GPBAMSEL register. Table 4-6. Alternate USB Function 4.5.5 GPIO GPBAMSEL SETTING USB FUNCTION GPIO42 GPBAMSEL[10] = 1b USB0DM GPIO43 GPBAMSEL[11] = 1b USB0DP High-Speed SPI Pin Muxing The SPI module on this device has a high-speed mode.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5 Specifications Absolute Maximum Ratings (1) (2) 5.1 over operating free-air temperature range (unless otherwise noted) Supply voltage MIN MAX VDDIO with respect to VSS –0.3 4.6 VDD3VFL with respect to VSS –0.3 4.6 VDDOSC with respect to VSS –0.3 4.6 UNIT V VDD with respect to VSS –0.3 1.5 Analog voltage VDDA with respect to VSSA –0.3 4.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.3 www.ti.com Recommended Operating Conditions MIN NOM MAX UNIT Device supply voltage, I/O, VDDIO (1) 3.14 3.3 3.47 V Device supply voltage, VDD 1.14 1.2 1.26 V Supply ground, VSS 0 Analog supply voltage, VDDA 3.14 Analog ground, VSSA S version (2) Q version (Q100 qualification) Free-Air temperature, TA (1) (2) 48 V 3.47 0 T version Junction temperature, TJ 3.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.4 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Power Consumption Summary Current values listed in this section are representative for the test conditions given and not the absolute maximum possible. The actual device currents in an application will vary with application code and pin configurations. Table 5-1 shows the device current consumption at 200-MHz SYSCLK. Table 5-1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.4.1 www.ti.com Current Consumption Graphs Figure 5-1 and Figure 5-2 are a typical representation of the relationship between frequency and current consumption/power on the device. The operational test from Table 5-1 was run across frequency at Vmax and high temperature. Actual results will vary based on the system implementation and conditions. 0.5 0.45 0.4 0.35 Current (A) 0.3 0.25 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Leakage current will increase with operating temperature in a nonlinear manner. The difference in VDD current between TYP and MAX conditions can be seen in Figure 5-3. The current consumption in HALT mode is primarily leakage current as there is no active switching if the internal oscillator has been powered down. Figure 5-3 shows the typical leakage current across temperature.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.4.2 www.ti.com Reducing Current Consumption The F2837xS devices provide some methods to reduce the device current consumption: • Any one of the four low-power modes—IDLE, STANDBY, HALT, and HIBERNATE—could be entered during idle periods in the application. • The flash module may be powered down if the code is run from RAM. • Disable the pullups on pins that assume an output function.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.5 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Electrical Characteristics over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER VOH High-level output voltage VOL Low-level output voltage IOH High-level output source current for all output pins IOL Low-level output sink current for all output pins VIH GPIO0–GPIO7, High-level input voltage GPIO42–GPIO43, GPIO46–GPIO47 (3.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.6 www.ti.com Thermal Resistance Characteristics 5.6.1 ZWT Package °C/W (1) AIR FLOW (lfm) (2) RΘJC Junction-to-case thermal resistance 8.3 N/A RΘJB Junction-to-board thermal resistance 11.6 N/A RΘJA (High k PCB) Junction-to-free air thermal resistance 21.5 0 19.0 150 17.8 250 16.5 500 0.2 0 0.3 150 0.4 250 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.6.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 PZP Package °C/W (1) AIR FLOW (lfm) (2) RΘJC Junction-to-case thermal resistance 4.3 N/A RΘJB Junction-to-board thermal resistance 5.9 N/A RΘJA (High k PCB) Junction-to-free air thermal resistance 19.1 0 14.3 150 RΘJMA Junction-to-moving air thermal resistance 12.8 250 11.4 500 PsiJT PsiJB (1) (2) Junction-to-package top Junction-to-board 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7 5.7.1 www.ti.com System Power Sequencing An external power supply must be used to supply 3.3 V to VDDIO, VDD3VFL, VDDOSC, and VDDA and to provide 1.2 V to VDD. The internal VREG is not supported; therefore, the VREGENZ pin must be tied high to 3.3 V. The supplies should ramp to full rail within 10 ms. Table 5-3 shows the supply ramp rate. Table 5-3.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.2.1 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Reset Sources The following reset sources exist on this device: XRS, WDRS, NMIWDRS, SYSRS, SCCRESET, and HIBRESET. See the Reset Signals table in the System Control chapter of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual. The parameter th(boot-mode) must account for a reset initiated from any of these sources.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com VDDIO, VDDA (3.3 V) VDD (1.2 V) tw(RSL1) XRS (A) Boot ROM CPU Execution Phase User-code th(boot-mode)(B) Boot-Mode Pins User-code dependent GPIO pins as input Boot-ROM execution starts Peripheral/GPIO function Based on boot code GPIO pins as input (pullups are disabled) I/O Pins User-code dependent A. B.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Clock Specifications 5.7.3.1 Clock Sources Table 5-6 lists four possible clock sources. Figure 5-7 provides an overview of the device's clocking system. Table 5-6. Possible Reference Clock Sources CLOCK SOURCE MODULES CLOCKED COMMENTS INTOSC1 Can be used to provide clock for: • Watchdog block • Main PLL • CPU-Timer 2 Internal oscillator 1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com INTOSC1 WDCLK CLKSRCCTL1 INTOSC2 SYSPLLCTL1 SYSCLKDIVSEL SYSCLK Divider OSCCLK X1(XTAL) System PLL To watchdog timer PLLRAWCLK SYSCLK CPU PLLSYSCLK To GS RAMs, GPIOs, and NMIWDs CPU1.CPUCLK To local memories CPU1.SYSCLK To ePIEs, LS RAMs, CLA message RAMs, and DCSMs One per SYSCLK peripheral PCLKCRx PERx.SYSCLK To peripherals PERx.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.3.2 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Clock Frequencies, Requirements, and Characteristics This section provides the frequencies and timing requirements of the input clocks, PLL lock times, frequencies of the internal clocks, and the frequency and switching characteristics of the output clock. 5.7.3.2.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.7.3.2.2 Internal Clock Frequencies Table 5-12 provides the clock frequencies for the internal clocks. Table 5-12.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.3.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Input Clocks and PLLs In addition to the internal 0-pin oscillators, multiple external clock source options are available. Figure 5-8 shows the recommended methods of connecting crystals, resonators, and oscillators to pins X1/X2 (also referred to as XTAL) and AUXCLKIN.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.3.4 www.ti.com Crystal Oscillator When using a quartz crystal, it may be necessary to include a damping resistor (RD) in the crystal circuit to prevent over-driving the crystal (drive level can be found in the crystal data sheet). In higher-frequency applications (10 MHz or greater), RD is generally not required.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.3.5 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Internal Oscillators To reduce production board costs and application development time, all F2837xS devices contain two independent internal oscillators, referred to as INTOSC1 and INTOSC2. By default, both oscillators are enabled at power up. INTOSC2 is set as the source for the system reference clock (OSCCLK) and INTOSC1 is set as the backup clock source.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.4 www.ti.com Flash Parameters The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal to execution from RAM.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-21. Flash/OTP Endurance Nf Flash endurance for the array (write/erase cycles) MIN TYP 20000 50000 MAX UNIT cycles Table 5-22.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.5 www.ti.com Emulation/JTAG The JTAG port has five dedicated pins: TRST, TMS, TDI, TDO, and TCK. The TRST signal should always be pulled down through a 2.2-kΩ pulldown resistor on the board. This MCU does not support the EMU0 and EMU1 signals that are present on 14-pin and 20-pin emulation headers.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Distance between the header and the target should be less than 6 inches (15.24 cm). 2.2 kW TRST GND 1 TMS 3 TDI 100 W MCU 5 3.3V 7 TDO 9 11 TCK TMS TRST TDI TDIS PD KEY TDO GND RTCK GND TCK GND 2 4 GND 6 8 10 12 4.7 kW 4.7 kW 13 3.3 V 15 open drain A low pulse from the emulator can be tied with other reset sources to reset the board.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.5.1 www.ti.com JTAG Electrical Data and Timing Table 5-23 lists the JTAG timing requirements. Table 5-24 lists the JTAG switching characteristics. Figure 5-11 shows the JTAG timing. Table 5-23. JTAG Timing Requirements NO. MIN MAX UNIT 1 tc(TCK) Cycle time, TCK 66.66 ns 1a tw(TCKH) Pulse duration, TCK high (40% of tc) 26.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.6 SPRS881C – AUGUST 2014 – REVISED MAY 2016 GPIO Electrical Data and Timing The peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. On reset, GPIO pins are configured as inputs. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.6.2 www.ti.com GPIO - Input Timing Table 5-26 shows the general-purpose input timing requirements. Figure 5-13 shows the sampling mode. Table 5-26.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.6.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLK.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.7 www.ti.com Interrupts Figure 5-15 provides a high-level view of the interrupt architecture. As shown in Figure 5-15, the devices support five external interrupts (XINT1 to XINT5) that can be mapped onto any of the GPIO pins. In this device, 16 ePIE block interrupts are grouped into 1 CPU interrupt. In total, there are 12 CPU interrupt groups, with 16 interrupts per group. CPU1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.7.1 SPRS881C – AUGUST 2014 – REVISED MAY 2016 External Interrupt (XINT) Electrical Data and Timing Table 5-27 lists the external interrupt timing requirements. Table 5-28 lists the external interrupt switching characteristics. Figure 5-16 shows the external interrupt timing. Table 5-27.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.8 www.ti.com Low-Power Modes This device has three clock-gating low-power modes and a special power-gating mode. Further details, as well as the entry and exit procedure, for all of the low-power modes can be found in the Low Power Modes section of the TMS320F2837xS Delfino Microcontrollers Technical Reference Manual. 5.7.8.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.8.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Low-Power Mode Wakeup Timing Table 5-31 shows the IDLE mode timing requirements, Table 5-32 shows the switching characteristics, and Figure 5-17 shows the timing diagram for IDLE mode. Table 5-31.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-33 shows the STANDBY mode timing requirements, Table 5-34 shows the switching characteristics, and Figure 5-18 shows the timing diagram for STANDBY mode. Table 5-33.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 (C) (A) (B) Device Status (F) (D)(E) STANDBY STANDBY (G) Normal Execution Flushing Pipeline Wake-up Signal tw(WAKE-INT) td(WAKE-STBY) OSCCLK XCLKOUT td(IDLE-XCOS) A. B. C. D. E. F. G. IDLE instruction is executed to put the device into STANDBY mode. The LPM block responds to the STANDBY signal, SYSCLK is held for a maximum 16 INTOSC1 clock cycles before being turned off.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-35 shows the HALT mode timing requirements, Table 5-36 shows the switching characteristics, and Figure 5-19 shows the timing diagram for HALT mode. Table 5-35.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 (C) (A) (B) Device Status (F) (D)(E) HALT (G) HALT Flushing Pipeline Normal Execution GPIOn td(WAKE-HALT) tw(WAKE-GPIO) OSCCLK Oscillator Start-up Time XCLKOUT td(IDLE-XCOS) A. B. C. D. E. F. G. H. IDLE instruction is executed to put the device into HALT mode.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-37 shows the HIBERNATE mode timing requirements, Table 5-38 shows the switching characteristics, and Figure 5-20 shows the timing diagram for HIBERNATE mode. Table 5-37. HIBERNATE Mode Timing Requirements MIN MAX UNIT tw(HIBWAKE) Pulse duration, HIBWAKE signal 40 µs tw(WAKEXRS) Pulse duration, XRS wake-up signal 40 µs Table 5-38.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.9 www.ti.com External Memory Interface (EMIF) The EMIF provides a means of connecting the CPU to various external storage devices like asynchronous memories (SRAM, NOR flash) or synchronous memory (SDRAM). 5.7.9.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.7.9.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 EMIF Electrical Data and Timing 5.7.9.3.1 Asynchronous RAM Table 5-39 shows the EMIF asynchronous memory timing requirements. Table 5-40 shows the EMIF asynchronous memory switching characteristics. Figure 5-21 through Figure 5-24 show the EMIF asynchronous memory timing diagrams. Table 5-39. EMIF Asynchronous Memory Timing Requirements NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-40. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued) NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 3 1 EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxDQM[y:0] 4 8 5 9 6 29 7 30 10 EMxOE 13 12 EMxD[y:0] EMxWE Figure 5-21. Asynchronous Memory Read Timing SETUP Extended Due to EMxWAIT STROBE STROBE HOLD EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxD[y:0] 14 11 EMxOE 2 EMxWAIT Asserted 2 Deasserted Figure 5-22.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 15 1 EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxDQM[y:0] 16 17 18 19 20 21 24 22 23 EMxWE 27 26 EMxD[y:0] EMxOE Figure 5-23. Asynchronous Memory Write Timing SETUP Extended Due to EMxWAIT STROBE STROBE HOLD EMxCS[y:2] EMxBA[y:0] EMxA[y:0] EMxD[y:0] 28 25 EMxWE 2 EMxWAIT Asserted 2 Deasserted Figure 5-24.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.7.9.3.2 Synchronous RAM Table 5-41 shows the EMIF synchronous memory timing requirements. Table 5-42 shows the EMIF synchronous memory switching characteristics. Figure 5-25 and Figure 5-26 show the synchronous memory timing diagrams. Table 5-41. EMIF Synchronous Memory Timing Requirements NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com BASIC SDRAM READ OPERATION 1 2 2 EMxCLK 4 3 EMxCS[y:2] 6 5 EMxDQM[y:0] 7 8 7 8 EMxBA[y:0] EMxA[y:0] 19 2 EM_CLK Delay 17 20 18 EMxD[y:0] 11 12 EMxRAS 13 14 EMxCAS EMxWE Figure 5-25.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 BASIC SDRAM WRITE OPERATION 1 2 2 EMxCLK 4 3 EMxCS[y:2] 6 5 EMxDQM[y:0] 7 8 7 8 EMxBA[y:0] EMxA[y:0] 9 10 EMxD[y:0] 11 12 EMxRAS 13 EMxCAS 15 16 EMxWE Figure 5-26.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.8 www.ti.com Analog Peripherals This analog subsystem module is described in this section. The analog modules on this device include the ADC, temperature sensor, buffered DAC, and CMPSS.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.8.1 www.ti.com Analog-to-Digital Converter (ADC) The ADCs on this device are successive approximation (SAR) style ADCs with selectable resolution of either 16 bits or 12 bits. There are multiple ADC modules which allow simultaneous sampling.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Figure 5-30 shows the ADC module block diagram.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.8.1.1 www.ti.com ADC Electrical Data and Timing Table 5-43 shows the ADC operating conditions for 16-bit differential mode. Table 5-44 shows the ADC characteristics for 16-bit differential mode. Table 5-45 shows the ADC operating conditions for 12-bit single-ended mode. Table 5-46 shows the ADC characteristics for 12-bit single-ended mode.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-44. ADC Characteristics (16-Bit Differential Mode) over recommended operating conditions (unless otherwise noted) (1) PARAMETER TEST CONDITIONS ADC conversion cycles (2) MIN TYP 29.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-45. ADC Operating Conditions (12-Bit Single-Ended Mode) over recommended operating conditions (unless otherwise noted) MIN ADCCLK (derived from PERx.SYSCLK) TYP 5 Sample window duration (set by ACQPS and PERx.SYSCLK) MAX UNIT 50 MHz 75 ns 1 ADCCLK VREFHI 2.4 2.5 or 3.0 VDDA V VREFLO VSSA 0 VSSA V 2.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-46. ADC Characteristics (12-Bit Single-Ended Mode) over recommended operating conditions (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN ADC conversion cycles (2) TYP 10.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-47. ADCEXTSOC Timing Requirements (1) MIN tw(INT) (1) Pulse duration, INT input low/high MAX UNIT Synchronous 2tc(SYSCLK) cycles With qualifier tw(IQSW) + tw(SP) + 1tc(SYSCLK) cycles For an explanation of the input qualifier parameters, see Table 5-26. 5.8.1.1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-50 shows the parasitic capacitance on each channel. Also, enabling a comparator adds approximately 1.4 pF of capacitance on positive comparator inputs and 2.5 pF of capacitance on negative comparator inputs. Table 5-50. Per-Channel Parasitic Capacitance ADC CHANNEL Cp (pF) COMPARATOR DISABLED COMPARATOR ENABLED ADCINA0 12.9 N/A ADCINA1 10.3 N/A ADCINA2 5.9 7.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.8.1.1.2 ADC Timing Diagrams Table 5-51 shows the ADC timings in 12-bit mode (SYSCLK cycles). Table 5-52 shows the ADC timings in 16-bit mode. Figure 5-33 and Figure 5-34 show the ADC conversion timings for two SOCs given the following assumptions: • SOC0 and SOC1 are configured to use the same trigger. • No other SOCs are converting or pending when the trigger occurs.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-51. ADC Timings in 12-Bit Mode (SYSCLK Cycles) ADCCLK PRESCALE ADCCTL2 [PRESCALE] ADCCLK CYCLES SYSCLK CYCLES RATIO ADCCLK:SYSCLK tEOC tLAT 0 1 11 13 1 1.5 2 2 21 23 3 2.5 26 4 3 31 5 3.5 6 tINT(EARLY) tINT(LATE) tEOC 1 11 11.0 1 21 10.5 28 1 26 10.4 34 1 31 10.3 36 39 1 36 10.3 4 41 44 1 41 10.3 7 4.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-52. ADC Timings in 16-Bit Mode ADCCLK PRESCALE ADCCTL2 [PRESCALE] ADCCLK CYCLES SYSCLK CYCLES RATIO ADCCLK:SYSCLK tEOC tLAT 0 1 31 32 1 1.5 2 2 60 61 3 2.5 75 4 3 90 5 3.5 6 tINT(EARLY) tINT(LATE) tEOC 1 31 31.0 1 60 30.0 75 1 75 30.0 91 1 90 30.0 104 106 1 104 29.7 4 119 120 1 119 29.8 7 4.5 134 134 1 134 29.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.8.1.2 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Temperature Sensor Electrical Data and Timing The temperature sensor can be used to measure the device junction temperature. The temperature sensor is sampled through an internal connection to the ADC and translated into a temperature through TI-provided software. When sampling the temperature sensor, the ADC must meet the acquisition time in Table 5-53. Table 5-53.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.8.2 www.ti.com Comparator Subsystem (CMPSS) Each CMPSS module includes two comparators, two internal voltage reference DACs (CMPSS DACs), two digital glitch filters, and one ramp generator. There are two inputs, CMPINxP and CMPINxN. Each of these inputs will be internally connected to an ADCIN pin. The CMPINxP pin is always connected to the positive input of the CMPSS comparators.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.8.2.1 www.ti.com CMPSS Electrical Data and Timing Table 5-54 shows the comparator electrical characteristics. Figure 5-37 shows the CMPSS comparator input referred offset. Figure 5-38 shows the CMPSS comparator hysteresis. Table 5-54.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-55 shows the CMPSS DAC static electrical characteristics. Figure 5-39 shows the CMPSS DAC static offset. Figure 5-40 shows the CMPSS DAC static gain. Figure 5-41 shows the CMPSS DAC static linearity. Table 5-55.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Ideal Gain Actual Gain Actual Linear Range Figure 5-40. CMPSS DAC Static Gain Linearity Error Figure 5-41.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.8.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Buffered Digital-to-Analog Converter (DAC) The buffered DAC module consists of an internal reference DAC and an analog output buffer that is capable of driving an external load. An integrated pulldown resistor on the DAC output helps to provide a known pin voltage when the output buffer is disabled.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.8.3.1 www.ti.com Buffered DAC Electrical Data and Timing Table 5-56 shows the buffered DAC electrical characteristics. Figure 5-43 shows the buffered DAC offset. Figure 5-44 shows the buffered DAC gain. Figure 5-45 shows the buffered DAC linearity. Table 5-56.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Offset Error Code 2048 Figure 5-43. Buffered DAC Offset Actual Gain Ideal Gain Code 3722 Code 373 Linear Range (3.3-V Reference) Figure 5-44.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Linearity Error Code 3722 Code 373 Linear Range (3.3-V Reference) Figure 5-45.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.9 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Control Peripherals NOTE For the actual number of each peripheral on a specific device, see Table 3-1. 5.9.1 Enhanced Capture (eCAP) The eCAP module can be used in systems where accurate timing of external events is important.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SYNC SPRS881C – AUGUST 2014 – REVISED MAY 2016 SYNCIn www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.9.1.1 SPRS881C – AUGUST 2014 – REVISED MAY 2016 eCAP Electrical Data and Timing Table 5-57 shows the eCAP timing requirement and Table 5-58 shows the eCAP switching characteristics. Table 5-57.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.9.2 www.ti.com Enhanced Pulse Width Modulator (ePWM) The ePWM peripheral is a key element in controlling many of the power electronic systems found in both commercial and industrial equipment.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 TBCTL2[SYNCOSELX] Time-Base (TB) Disable CTR=CPMC CTR=CPMD Rsvd TBPRD Shadow (24) TBPRDHR (8) TBPRD Active (24) 8 CTR=PRD 00 01 10 11 CTR=ZERO CTR=CMPB TBCTL[SWFSYNC] Sync Out Select EPWMxSYNCO EPWMxSYNCI TBCTL[PHSEN] TBCTL[SYNCOSEL] Counter Up/Down (16 Bit) (A) DCAEVT1.sync (A) DCBEVT1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 PIE(s), CLA(s) XINT5 XINT4 INPUT14 INPUT13 Input X-Bar INPUT1 INPUT2 INPUT3 INPUT4 INPUT5 INPUT6 GPIOx Async/ Sync/ Sync+Filter INPUT7 INPUT8 INPUT9 INPUT10 INPUT11 INPUT12 GPIO0 www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.9.2.1 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Control Peripherals Synchronization The ePWM and eCAP synchronization chain allows synchronization between multiple modules for the system. Figure 5-49 shows the synchronization chain architecture. EXTSYNCIN1 EXTSYNCIN2 EPWM1 EPWM1SYNCOUT EPWM2 EPWM4 EPWM3 EXTSYNCOUT EPWM4SYNCOUT Pulse-Stretched (8 PLLSYSCLK Cycles) EPWM5 SYNCSEL.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.9.2.2 www.ti.com ePWM Electrical Data and Timing Table 5-59 shows the PWM timing requirements and Table 5-60 shows the PWM switching characteristics. Table 5-59.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.9.2.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 External ADC Start-of-Conversion Electrical Data and Timing Table 5-62 shows the external ADC start-of-conversion switching characteristics. Figure 5-51 shows the ADCSOCAO or ADCSOCBO timing. Table 5-62.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.9.3 www.ti.com Enhanced Quadrature Encoder Pulse (eQEP) The eQEP module interfaces directly with linear or rotary incremental encoders to obtain position, direction, and speed information from rotating machines used in high-performance motion and positioncontrol systems.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.9.3.1 www.ti.com eQEP Electrical Data and Timing Table 5-63 lists the eQEP timing requirement and Table 5-64 lists the eQEP switching characteristics. Table 5-63.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 5.9.4 SPRS881C – AUGUST 2014 – REVISED MAY 2016 High-Resolution Pulse Width Modulator (HRPWM) The HRPWM combines multiple delay lines in a single module and a simplified calibration system by using a dedicated calibration delay line.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.9.5 www.ti.com Sigma-Delta Filter Module (SDFM) The SDFM is a four-channel digital filter designed specifically for current measurement and resolver position decoding in motor control applications. Each channel can receive an independent sigma-delta (ΣΔ) modulated bit stream. The bit streams are processed by four individually programmable digital decimation filters.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 SDFM- Sigma Delta Filter Module G4 Streams Filter Channel 1 R Comparator filter SD1_D1 Input Ctrl SD1_C1 Data filter SD1INT IEL IEH Interrupt Unit SD2INT PIE R FILRES PWM11.CMPC Filter Channel 2 SD1_D2 SD1_C2 FILRES SD1_D3 Filter Channel 3 Register Map Data bus SD1_C3 FILRES PWM11.CMPD SD1_D4 SD1_C4 Filter Channel 4 SD1FLT1.IEH SD1FLT1.IEL SD1FLT2.IEH SD1FLT2.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.9.5.1 www.ti.com SDFM Electrical Data and Timing Table 5-66 shows the SDFM timing requirements. Figure 5-54 through Figure 5-57 show the SDFM timing diagrams. Table 5-66.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Mode 2 (Manchester-encoded bit stream) tc(SDD)M2 Modulator internal clock tw(SDDH)M2 Modulator internal data 1 0 1 1 1 0 0 1 1 SDx-Dy Figure 5-56. SDFM Timing Diagram – Mode 2 Mode 3 (CLKx is driven externally) tc(SDC)M3 tw(SDCH)M3 SDx_Cy tsu(SDDV-SDCH)M3 th(SDCH-SDD)M3 SDx_Dy Figure 5-57.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10 Communications Peripherals NOTE For the actual number of each peripheral on a specific device, see Table 3-1. 5.10.1 Controller Area Network (CAN) NOTE The CAN module uses the IP known as D_CAN. This document uses the names CAN and D_CAN interchangeably to reference this peripheral.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.2 Inter-Integrated Circuit (I2C) The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Figure 5-58 shows how the I2C peripheral module interfaces within the device. 2 I C Module I2CXSR I2CDXR TX FIFO FIFO Interrupt to CPU/PIE SDA RX FIFO Peripheral Bus I2CRSR SCL Clock Synchronizer I2CDRR Control/Status Registers CPU Prescaler Noise Filters Interrupt to CPU/PIE I2C INT Arbitrator Figure 5-58.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.2.1 I2C Electrical Data and Timing Table 5-67 shows the I2C timing requirements. Table 5-68 shows the I2C switching characteristics. Table 5-67. I2C Timing Requirements MIN MAX UNIT th(SDA-SCL)START Hold time, START condition, SCL fall delay after SDA fall 0.6 µs tsu(SCL-SDA)START Setup time, Repeated START, SCL rise before SDA fall delay 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Figure 5-59 shows the block diagram of the McBSP module. TX Interrupt MXINT To CPU Peripheral Write Bus TX Interrupt Logic 16 16 DXR2 Transmit Buffer DXR1 Transmit Buffer McBSP Transmit Interrupt Select Logic PERx.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.3.1 McBSP Electrical Data and Timing 5.10.3.1.1 McBSP Transmit and Receive Timing Table 5-69 shows the McBSP timing requirements. Table 5-70 shows the McBSP switching characteristics. Figure 5-60 and Figure 5-61 show the McBSP timing diagrams. Table 5-69. McBSP Timing Requirements (1) (2) NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-70. McBSP Switching Characteristics (1) (2) over recommended operating conditions (unless otherwise noted) NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com M1, M11 M2, M12 M13 M3, M12 CLKR M4 M4 M14 FSR (int) M15 M16 FSR (ext) M18 M17 DR (RDATDLY=00b) Bit (n−1) (n−2) (n−3) M17 (n−4) M18 DR (RDATDLY=01b) Bit (n−1) (n−2) (n−3) M17 M18 DR (RDATDLY=10b) Bit (n−1) (n−2) Figure 5-60.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.3.1.2 McBSP as SPI Master or Slave Timing For CLKSTP = 10b and CLKXP = 0, Table 5-71 shows the timing requirements, Table 5-72 shows the switching characteristics, and Figure 5-62 shows the timing diagram. Table 5-71. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) (1) NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com For CLKSTP = 11b and CLKXP = 0, Table 5-73 shows the timing requirements, Table 5-74 shows the switching characteristics, and Figure 5-63 shows the timing diagram. Table 5-73. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) (1) MASTER NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 For CLKSTP = 10b and CLKXP = 1, Table 5-75 shows the timing requirements, Table 5-76 shows the switching characteristics, and Figure 5-64 shows the timing diagram. Table 5-75. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) (1) NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com For CLKSTP = 11b and CLKXP = 1, Table 5-77 shows the timing requirements, Table 5-78 shows the switching characteristics, and Figure 5-65 shows the timing diagram. Table 5-77. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) (1) MASTER NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.4 Serial Communications Interface (SCI) The SCI is a 2-wire asynchronous serial port, commonly known as a UART.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com SCICTL1.1 Frame Format and Mode Parity Even/Odd SCITXD TXSHF Register TXENA Enable SCICCR.6 SCICCR.5 TX EMPTY SCICTL2.6 8 TXRDY Transmitter-Data Buffer Register TX INT ENA SCICTL2.7 SCICTL2.0 TXWAKE SCICTL1.3 8 TX FIFO _0 1 SCITXD TX FIFO Interrupt TX FIFO _1 −−−−− TX Interrupt Logic TXINT To CPU TX FIFO _15 WUT SCI TX Interrupt select logic SCITXBUF.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 The major elements used in full-duplex operation include: • A transmitter (TX) and its major registers: – SCITXBUF register – Transmitter Data Buffer register. Contains data (loaded by the CPU) to be transmitted – TXSHF register – Transmitter Shift register.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5 Serial Peripheral Interface (SPI) The SPI is a high-speed synchronous serial input/output (I/O) port that allows a serial bit stream of programmed length (1 to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI is normally used for communications between the microcontroller and external peripherals or another controller.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 The SPI operates in master or slave mode. The master initiates data transfer by sending the SPICLK signal. For both the slave and the master, data is shifted out of the shift registers on one edge of the SPICLK and latched into the shift register on the opposite SPICLK clock edge. If the CLOCK PHASE bit (SPICTL.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5.1 SPI Electrical Data and Timing The following sections contain the SPI External Timings in Non-High-Speed Mode: Section 5.10.5.1.1 Master Mode External Timings Where Clock Phase = 0 Section 5.10.5.1.2 Master Mode External Timings Where Clock Phase = 1 Section 5.10.5.1.3 Slave Mode External Timings Where Clock Phase = 0 Section 5.10.5.1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.5.1.1 Master Mode External Timings Where Clock Phase = 0 Table 5-79 shows the SPI master mode external timings where (SPIBRR + 1) is even or SPIBRR = 0 or 2. Table 5-80 shows the SPI master mode external timings where (SPIBRR + 1) is odd and SPIBRR > 3. Figure 5-68 shows the SPI master mode external timing where the clock phase = 0. Table 5-79.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-80. SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3 NO. 1 MIN MAX 5tc(LSPCLK) 127tc(LSPCLK) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 Master In Data Must Be Valid SPISOMI 23 24 (A) SPISTE A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 5-68.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5.1.2 Master Mode External Timings Where Clock Phase = 1 Table 5-81 shows the SPI master mode external timings where (SPIBRR + 1) is even or SPIBRR = 0 or 2. Table 5-82 shows the SPI master mode external timings where (SPIBRR + 1) is odd or SPIBRR > 3. Figure 5-69 shows the SPI master mode external timing where the clock phase = 1. Table 5-81.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-82. SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3 NO. 1 MIN MAX 5tc(LSPCLK) 127tc(LSPCLK) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.5tc(LSPCLK) + 1 tw(SPCL))M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5.1.3 Slave Mode External Timings Where Clock Phase = 0 Table 5-83 and Figure 5-70 show the SPI slave mode external timings where the clock phase = 0. Table 5-83. SPI Slave Mode External Timings Where Clock Phase = 0 NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 SPISOMI 16 SPISOMI Data Is Valid 19 20 SPISIMO Data Must Be Valid SPISIMO 25 26 SPISTE Figure 5-70.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5.1.4 Slave Mode External Timings Where Clock Phase = 1 Table 5-84 and Figure 5-71 show the SPI slave mode external timings where the clock phase = 1. Table 5-84. SPI Slave Mode External Timings Where Clock Phase = 1 NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.5.1.5 High-Speed Master Mode External Timings Where Clock Phase = 0 Table 5-85 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is even or SPIBRR = 0 or 2. Table 5-86 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is odd and SPIBRR > 3. Figure 5-72 shows the high-speed SPI master mode external timing where the clock phase = 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 5-86. High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd and SPIBRR > 3 NO. 1 MIN MAX 5tc(LSPCLK) 127tc(LSPCLK) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.5tc(LSPCLK) + 1 tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 Master In Data Must Be Valid SPISOMI 23 24 (A) SPISTE A. On the trailing end of the word, SPISTE will go inactive except between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 5-72.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5.1.6 High-Speed Master Mode External Timings Where Clock Phase = 1 Table 5-87 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is even or SPIBRR = 0 or 2. Table 5-88 shows the high-speed SPI master mode external timings where (SPIBRR + 1) is odd or SPIBRR > 3. Figure 5-73 shows the high-speed SPI master mode external timing where the clock phase = 1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 5-88. High-Speed SPI Master Mode External Timings Where (SPIBRR + 1) is Odd or SPIBRR > 3 NO. 1 MIN MAX 5tc(LSPCLK) 127tc(LSPCLK) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 0.5tc(LSPCLK) – 1 0.5tc(SPC)M – 0.5tc(LSPCLK) + 1 tw(SPCL))M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M + 0.5tc(LSPCLK) – 1 0.5tc(SPC)M + 0.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5.1.7 High-Speed Slave Mode External Timings Where Clock Phase = 0 Table 5-89 and Figure 5-74 show the high-speed SPI slave mode external timings where the clock phase = 0. Table 5-89. High-Speed SPI Slave Mode External Timings Where Clock Phase = 0 NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 SPISOMI 16 SPISOMI Data Is Valid 19 20 SPISIMO Data Must Be Valid SPISIMO 25 26 SPISTE Figure 5-74.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.5.1.8 High-Speed Slave Mode External Timings Where Clock Phase = 1 Table 5-90 and Figure 5-75 show the high-speed SPI slave mode external timings where the clock phase = 1. Table 5-90. High-Speed SPI Slave Mode External Timings Where Clock Phase = 1 NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.6 Universal Serial Bus (USB) Controller The USB controller operates as a full-speed or low-speed function controller during point-to-point communications with USB host or device functions. The USB module has the following features: • USB 2.0 full-speed (12 Mbps) and low-speed (1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 5.10.6.1 USB Electrical Data and Timing Table 5-91 shows the USB input ports DP and DM timing requirements. Table 5-92 shows the USB output ports DP and DM switching characteristics. Table 5-91. USB Input Ports DP and DM Timing Requirements MIN MAX V(CM) Differential input common mode range 0.8 2.5 UNIT Z(IN) Input impedance 300 VCRS Crossover voltage 1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.7 Universal Parallel Port (uPP) Interface The uPP interface is a high-speed parallel interface with dedicated data lines and minimal control signals. The uPP interface is designed to interface cleanly with high-speed ADCs or DACs with 8-bit data width.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com The uPP interface supports the following: • Mainstream high-speed data converters with parallel conversion interface. • Mainstream high-speed streaming interface with frame START indication. • Mainstream high-speed streaming interface with data ENABLE indication. • Mainstream high-speed streaming interface with synchronization WAIT signal.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 5.10.7.1 uPP Electrical Data and Timing Table 5-93 shows the uPP timing requirements. Table 5-94 shows the uPP switching characteristics. Figure 5-79 through Figure 5-82 show the uPP timing diagrams. Table 5-93. uPP Timing Requirements NO.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 1 2 3 CLK 4 5 START 6 7 ENABLE WAIT 8 9 DATA[n:0] Data1 Data2 Data3 Data4 Data5 Data7 Data6 Data8 Data9 Figure 5-79. uPP Single Data Rate (SDR) Receive Timing 1 2 3 CLK 4 5 START 6 7 ENABLE WAIT 8 DATA[n:0] I1 Q1 I2 Q2 I3 Q3 10 9 I4 Q4 I5 Q5 I6 Q6 I7 11 Q7 I8 Q8 I9 Q9 Figure 5-80.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 12 13 14 CLK 15 START 16 ENABLE 19 20 WAIT 17 DATA[n:0] Data1 Data2 Data3 Data4 Data5 Data6 Data7 Data8 Data9 Figure 5-81. uPP Single Data Rate (SDR) Transmit Timing 12 13 14 CLK 15 START 16 ENABLE 21 22 WAIT 17 DATA[n:0] I1 18 Q1 I2 Q2 I3 Q3 I4 Q4 I5 Q5 I6 Q6 I7 Q7 I8 Q8 I9 Q9 Figure 5-82.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 6 Detailed Description 6.1 Overview The Delfino TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such as industrial drives and servo motor control; solar inverters and converters; digital power; transportation; and power line communications.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 MEMCPU1 CPU1.CLA1 to CPU1 128x16 MSG RAM CPU1 to CPU1.CLA1 128x16 MSG RAM CPU1.CLA1 C28 CPU-1 Dual Code Security Module + Emulation Code Security Logic (ECSL) CPU1 Local Shared 6x 2Kx16 LS0-LS5 RAMs Secure Memories shown in Red CPU1.D0 RAM 2Kx16 CPU1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 6.3 www.ti.com Memory 6.3.1 C28x Memory Map The C28x memory map is described in Table 6-1. Memories accessible by the CLA or DMA (direct memory access) are noted as well. Table 6-1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.3.2 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Flash Memory Map The F28379S, F28377S, and F28375S devices have two flash banks [512KB (256KW) each] for a total of 1MB (512KW). Only one bank can be programmed or erased at a time. The Flash API can be executed from RAM, or since there are two Flash banks for one CPU, the Flash API code can be executed from one bank to erase/program the other bank.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 6-2.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.3.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 EMIF Chip Select Memory Map The EMIF memory map is shown in Table 6-4. Table 6-4.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Table 6-5.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 Table 6-5.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 6.3.5 www.ti.com Memory Types Table 6-6 provides more information about each memory type. Table 6-6.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.3.5.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Global Shared RAM (GSx RAM) RAM blocks which are accessible from both the CPU and DMA are called global shared RAMs (GSx RAMs). Both the CPU and DMA have full read and write access to these memories. All GSx RAM blocks have parity. The GSx RAMs have access protection (CPU write/CPU fetch/DMA write). 6.3.5.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 6.4 www.ti.com Identification Table 6-8 shows the Device Identification Registers. Table 6-8.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.5 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Bus Architecture – Peripheral Connectivity Table 6-9 shows a broad view of the peripheral and configuration register accessibility from each bus master. Peripherals within peripheral frames 1 or 2 will all be mapped to the respective secondary master as a group (if SPI is assigned to CPU1.DMA, then McBSP is also assigned to CPU1.DMA). Table 6-9.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 6.6 www.ti.com C28x Processor The CPU is a 32-bit fixed-point processor. This device draws from the best features of digital signal processing; reduced instruction set computing (RISC); and microcontroller architectures, firmware, and tool sets. The CPU features include a modified Harvard architecture and circular addressing.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.6.3 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Viterbi, Complex Math, and CRC Unit II The VCU-II is the second-generation Viterbi, Complex Math, and CRC extension to the C28x CPU. The VCU-II extends the capabilities of the C28x CPU by adding registers and instructions to accelerate the performance of Fast Fourier Transforms (FFTs) and communications-based algorithms.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 6.7 www.ti.com Control Law Accelerator The CLA is an independent single-precision (32-bit) FPU processor with its own bus structure, fetch mechanism, and pipeline. Eight individual CLA tasks can be specified. Each task is started by software or a peripheral such as the ADC, ePWM, eCAP, eQEP, or CPU Timer 0. The CLA executes one task at a time to completion.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.8 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Direct Memory Access The CPU has its own 6-channel DMA module. The DMA module provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com Figure 6-3 shows a device-level block diagram of the DMA. ADC RESULTS (4) XINT (5) TIMER (3) Global Shared 16x 4Kx16 GS0-15 RAMs C28x Bus DMA Bus TINT (0-2) XINT (1-5) ADC INT (A-D) (1-4), EVT (A-D) SDxFLTy (x = 1 to 2, y = 1 to 4) SOCA (1-12), SOCB (1-12) MXEVT (A-B), MREVT (A-B) SPITX (A-C), SPIRX (A-C) DMA Trigger Source Selection DMACHSRCSEL1.CHx DMACHSRCSEL2.CHx CHx.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.9 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Boot ROM and Peripheral Booting The device boot ROM contains bootloading software. The device boot ROM is executed each time the device comes out of reset. Users can configure the device to boot to flash (using GET mode) or choose to boot the device through one of the bootable peripherals by configuring the boot mode GPIO pins.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 6.9.1 www.ti.com EMU Boot or Emulation Boot The CPU enters this boot when it detects that TRST is HIGH (in other words, when an emulator/debugger is connected). In this mode, the user can program the EMUBOOTCTRL register (at location 0xD00) to instruct the device on how to boot. If the contents of the EMUBOOTCTRL locations are invalid, then the device would default into WAIT Boot mode.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 6.9.4 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Peripheral Pins Used by Bootloaders Table 6-14 shows the GPIO pins used by each peripheral bootloader. This device supports two sets of GPIOs for each mode, as shown in Table 6-14. Table 6-14.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 6.10 Dual Code Security Module The dual code security module (DCSM) prevents access to on-chip secure memories. The term “secure” means access to secure memories and resources is blocked. The term “unsecure” means access is allowed; for example, through a debugging tool such as Code Composer Studio™ (CSS).
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 6.13 Watchdog The watchdog module is the same as the one on previous TMS320C2000 devices, but with an optional lower limit on the time between software resets of the counter. This windowed countdown is disabled by default, so the watchdog is fully backwards-compatible. The watchdog generates either a reset or an interrupt.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 7 Applications, Implementation, and Layout NOTE Information in the following sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 7.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 8 Device and Documentation Support 8.1 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ MCU devices and support tools. Each TMS320 MCU commercial family member has one of three prefixes: TMX, TMP, or TMS (for example, TMS320F28379S).
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 TMS 320 F www.ti.com 28379S PTP T PREFIX TMX = experimental device TMP = prototype device TMS = qualified device DEVICE FAMILY 320 = TMS320 MCU Family TEMPERATURE RANGE T = −40°C to 105°C (TJ) S = −40°C to 125°C (TJ) Q = −40°C to 125°C (TA) (Q refers to Q100 qualification for automotive applications.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com SPRS881C – AUGUST 2014 – REVISED MAY 2016 F021 Flash Application Programming Interface (API) The F021 Flash Application Programming Interface (API) provides a software library of functions to program, erase, and verify F021 on-chip Flash memory.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 8.3 www.ti.com Documentation Support To receive notification of documentation updates—including silicon errata—go to the product folder for your device on ti.com (TMS320F28379S, TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S). In the upper right-hand corner, click the "Alert me" button.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S www.ti.com 8.4 SPRS881C – AUGUST 2014 – REVISED MAY 2016 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-1.
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TMS320F28379S, TMS320F28377S TMS320F28376S, TMS320F28375S, TMS320F28374S SPRS881C – AUGUST 2014 – REVISED MAY 2016 www.ti.com 9 Mechanical Packaging and Orderable Information 9.1 Packaging Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Oct-2016 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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STANDARD TERMS AND CONDITIONS FOR EVALUATION MODULES 1. Delivery: TI delivers TI evaluation boards, kits, or modules, including any accompanying demonstration software, components, or documentation (collectively, an “EVM” or “EVMs”) to the User (“User”) in accordance with the terms and conditions set forth herein. Acceptance of the EVM is expressly subject to the following terms and conditions. 1.
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FCC Interference Statement for Class B EVM devices NOTE: This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications.
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【無線電波を送信する製品の開発キットをお使いになる際の注意事項】開発キットの中には技術基準適合証明を受けていないものがあります。技術適合証明を受けていないもののご使用に際しては、電波法遵守のため、以下のいずれかの措置を取っていただく必要がありますのでご注意ください。 1. 2. 3. 電波法施行規則第6条第1項第1号に基づく平成18年3月28日総務省告示第173号で定められた電波暗室等の試験設備でご使用いただく。実験局の免許を取得後ご使用いただく。技術基準適合証明を取得後ご使用いただく。なお、本製品は、上記の「ご使用にあたっての注意」を譲渡先、移転先に通知しない限り、譲渡、移転できないものとします。上記を遵守頂けない場合は、電波法の罰則が適用される可能性があることをご留意ください。日本テキサス・インスツルメンツ株式会社東京都新宿区西新宿６丁目２４番１号西新宿三井ビル 3.3.3 Notice for EVMs for Power Line Communication: Please see http://www.tij.co.
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SPACER 6. Disclaimers: 6.1 EXCEPT AS SET FORTH ABOVE, EVMS AND ANY WRITTEN DESIGN MATERIALS PROVIDED WITH THE EVM (AND THE DESIGN OF THE EVM ITSELF) ARE PROVIDED "AS IS" AND "WITH ALL FAULTS." TI DISCLAIMS ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, REGARDING SUCH ITEMS, INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADE SECRETS OR OTHER INTELLECTUAL PROPERTY RIGHTS. 6.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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LAUNCHXL-F28377S Overview User's Guide Literature Number: SPRUI25A June 2015 – Revised June 2015
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Contents 1 2 3 Introduction ......................................................................................................................... 4 Kit Contents ........................................................................................................................ 5 Installation .......................................................................................................................... 5 4 Getting Started with the LAUNCHXL-F28377S........................................
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www.ti.com List of Figures 1 LAUNCHXL-F28377S Board Overview ................................................................................... 5 2 LAUNCHXL-F28377S_B Block Diagram Schematic 3 4 5 6 7 8 9 10 11 12 13 .................................................................. LAUNCHXL-F28377S XDS100v2 Schematic .......................................................................... LAUNCHXL-F28377S Power Schematic .............................................................................
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User's Guide SPRUI25A – June 2015 – Revised June 2015 LAUNCHXL-F28377S Overview 1 Introduction The C2000™ Delfino™ LaunchPad™, LAUNCHXL-F28377S, is a complete low-cost development board for the Texas Instruments Delfino F2837xS devices. The LAUNCHXL-F28377S kit features all the hardware and software necessary to develop applications based on the F2837xS microprocessor.
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Kit Contents www.ti.com Figure 1. LAUNCHXL-F28377S Board Overview 2 Kit Contents The LAUNCHXL-F28377S LaunchPad experimenter kit includes the following items: • C2000 Delfino LaunchPad Board (LAUNCHXL-F28377S) • Mini USB-B Cable, 0.5m • Quick Start Guide 3 Installation The F28377S LaunchPad is supported in Code Composer Studio. 3.1 3.1.
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Getting Started with the LAUNCHXL-F28377S 3.1.3 www.ti.com Install the Hardware After Code Composer Studio is installed, plug the supplied USB cable into the C2000 LaunchPad board and into an available USB port on your computer. Windows® will automatically detect the hardware and ask you to install software drivers. Let Windows run a search for the drivers and automatically install them.
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Hardware Configuration www.ti.com 5 Hardware Configuration The F28377S LaunchPad provides users with several options on how to configure the board. 5.1 ADC Resolution While the F28377S device has a 16 bit ADC, this development kit has been designed to use the ADC in its 12-bit mode. The user can use the ADC in its 16-bit mode by driving the proper differential signals into the ADC.
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LAUNCHXL-F28377S Hardware www.ti.com 6 LAUNCHXL-F28377S Hardware 6.1 Device Pin Out .Table 1 through Table 4 lists the pin out and pin mux options for the C2000 LaunchPad. Additional muxing options are available and can be found in the TMS320F2837xS Delfino Microcontrollers Data Manual (SPRS881). Table 1. F28377S LaunchPad Pin Out and Pin Mux Options - J1, J3 Mux Value 3 2 Mux Value 1 J1 Pin J3 Pin +3.
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LAUNCHXL-F28377S Hardware www.ti.com Table 3. F28377S LaunchPad Pin Out and Pin Mux Options - J5, J7 Mux Value 3 2 Mux Value 1 0 J5 Pin J7 Pin 0 +3.3V 41 61 +5V NC 42 62 GND EM1RAS EM1A14 GPIO87 43 63 ADCIN15 EM1CAS EM1A13 GPIO86 44 64 ADCINA2 NC 45 65 ADCINA5 NC 46 66 ADCINB5 GPIO65 47 67 ADCINA3 EM1D19 NC 48 68 ADCINB3 EM1D15 GPIO69 49 69 ADCINA4 EM1D18 GPIO66 50 70 NC 1 2 3 2 3 Table 4.
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10 LAUNCHXL-F28377S Overview Copyright © 2015, Texas Instruments Incorporated E D C DATA 20150326 REV REV1.0 NOTE ORIGINAL RELEASED Sheet 2 Micro USB type B Sheet 3 Power management 2 Sheet 2 4 SERIAL 1&2 CAN Sheet 6 TMS320F28377S LEDS Sheet 5 FT2232H Sheet 4 & 5 3 LAUNCHXL-F28377S Document Number: BLOCK DIAGRAM Date: 6/22/2015 9:21:57 AM TITLE: Note: DNP = Do Not Populate BoosterPack 2 Connector Sheet 6 BoosterPack 1 Connector Sheet 6 QEP Connector Sheet 6 5 REV: 1.
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E D C B A 4 5 FTDI_CS CS CLK DD+ GND DO 1 VCC TP14TP15TP16TP17 AGND 93LC56BT-I/OT AGND 2.2k R31 AGND 0.1u C43 P$49 C18 36p C17 36p 12M FTDI_DATA Q3 P$7 P$6 P$14 P$8 P$13 P$3 P$2 P$63 P$62 P$61 AGND FTDI_CS FTDI_CLK FTDI_DATA 1K R22 D+ D- FTDI_3V3 P$50 FTDI_1V8 0.1u 0.1u 0.1u 3.3u TP11 FTDI_3V3 100K22uF R47 C45 2.
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E D C B A GND 4.7u C8 +3V3 GND 2.2u C72 +3V3 GND 10u 4 5 GND GND P$6 P$7 P$5 P$4 R54 64.9k R55 39.2k 3.3uH CDRH3D16/HPNP-3R3NC SD VIN 22u C80 GND +1V2 GND 2.2u C29 +3V3 FB SWITCH 3 1 GND 2.2u C27 VDDA 1N5819HW-7-F D3 L3 60Ohm GND 820p GND 2.2u C2 +3V3 3 GND C41 10uF +5V C25 10u C81 GND L11 220Ohm GND GND GND GND GND GND GND L6 L8 1u 2 C60 0.1u C61 0.1u U12 LMR62421XMFE/NOPB 2.
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E D C 1 0 0 0 0 TRST x 0 0 1 1 x 0 1 0 1 1 2 3 S1 VSSOSC GPIO84 GPIO72 TRST BOOT GND 64 TH 67 17*3 GND GND GND 2.2k Emulation Boot Parallel I/O SCI Wait GetMode 204-3ST GPIO72 GPIO84 6 5 4 JTAG_TRST 820 +3V3 +3V3 R5 820 B TMS320F28377S R4 C26 0.1u GND VREGENZ VDD VSS VDD3VFL VSSOSC VDDA VSSA VDDIO VDDOSC R10 2.2k 16*9 41 R9 2.
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Copyright © 2015, Texas Instruments Incorporated E D C B TMS320F28377S C35 C34 C33 C36 R41 1K R40 1K R37 1K R36 1K 0.1u 0.1u 0.1u 0.1u GND GND GND GND DAC4 DAC3 DAC2 DAC1 PWM_DAC 51 73 74 GPIO41 GPIO42 GPIO43 5 GPIO19 GPIO18 GPIO21 GPIO20 C24 2Y 1Y 4 6 SN74LVC2G07 GND 2A 1A +3V3 +3V3 LAUNCHXL-F28377S 3 1 U9 Document Number: F28377S_B Date: 6/22/2015 9:21:57 AM TITLE: GPIO13 GPIO12 GND 0.
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E D C A B I PWR GND LAUNCHXL-F28377S Overview GND QEP_A 1 2 3 4 5 +5V 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 EQEP1A EQEP1B EQEP1I GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO20 GPIO21 DAC1 DAC2 GPIO60 GPIO61 GPIO43 GPIO42 GPIO71 GPIO90 GPIO89 GPIO41 DAC3 DAC4 GPIO2 GPIO3 GPIO10 GPIO11 GPIO18 GPIO19 GPIO69 GPIO66 GPIO65 GPIO87 GPIO86 +3V3 GND QEP_B 1 2 3 4 5 +5V 20 19 18 17 16 15 14 13 12 11 21 22 23 24 25 26 27 28 2
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LAUNCHXL-F28377S Hardware 6.3 www.ti.com PCB Layout Figure 8 through Figure 13 shows the LAUNCHXL-F28377S PCB layout. 16 Figure 8. Top Silk Figure 9. Top Copper Figure 10. Inner Copper 1 Figure 11. Inner Copper 2 Figure 12. Bottom Silk Figure 13.
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LAUNCHXL-F28377S Hardware www.ti.com 6.4 Bill of Materials (BOM) Table 5 lists the LAUNCHXL-F28377S bill of materials. Table 5. LAUNCHXL-F28377S Bill of Materials Item Ref Varient Qty Vendor Stk Number S3 All 1 SWITCH TACTILE SPST-NO 0.05A Omron Electronics Inc- B3F-3152 24 V EMC Div Digikey SW410-ND S1 All 1 SWITCH TAPE SEAL 3 POS SMD 50 V 219-3MST Digikey CT2193MST-ND F1 All 1 PTC RESETTABLE .50A 15 V 1812 Bourns Inc.
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LAUNCHXL-F28377S Hardware www.ti.com Table 5. LAUNCHXL-F28377S Bill of Materials (continued) Item 18 Ref Varient Qty Description Mfg Part Number Vendor Stk Number C8, C10, C11 All 3 CAP CER 4.7 µF 6.3 V 20% X5R 0402 Murata Electronics North America GRM155R60J475ME4 7D Digikey 490-5915-1-ND C6, C7, C19 All 3 CAP CER 1 µF 6.
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LAUNCHXL-F28377S Hardware www.ti.com Table 5. LAUNCHXL-F28377S Bill of Materials (continued) Item Ref Varient Qty Part Number Vendor Stk Number R54 All 1 Description RES SMD 64.9K Ω 1% 1/10W 0402 Panasonic Electronic Components Mfg ERJ-2RKF6492X Digikey P64.
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LAUNCHXL-F28377S Hardware www.ti.com Table 5. LAUNCHXL-F28377S Bill of Materials (continued) Item 20 Ref Varient Qty Description Mfg Part Number Vendor Stk Number U4 All 1 IC REG BUCK SYNC ADJ 1.2A 8WSON Texas Instruments TPS62080ADSGT Digikey 296-30360-1-ND U17 All 1 IC REG BUCK SYNC 3.
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References www.ti.com 7 References The following documents describe the C2000 devices. Copies of these documents are available on the Internet at http://www.ti.com/c2000 and www.ti.com/c2000-launchpad, or click on the links below: 1. TMS320F2837xS Delfino Microcontrollers Data Manual (SPRS881) 2. TMS320F28377S, TMS320F28376S, TMS320F28375S, TMS320F28374S Delfino Microcontrollers Silicon Errata (SPRZ422) 3. TMS320F2837xS Delfino Microcontrollers Technical Reference Guide (SPRUHX5) 4.
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Frequently Asked Questions (FAQ) 8 www.ti.com Frequently Asked Questions (FAQ) 1. Can other programming and debug tools (such as an XDS510 emulator) be used with the C2000 LaunchPad? While a user could potentially connect an external emulator to the F28377S device present on the LaunchPad, it would require some rework of the board. It is recommended that users who want to use an external emulator purchase a controlCard and docking station that includes an external JTAG connector. 2.
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Revision History www.ti.com Revision History Changes from Original (June 2015) to A Revision ......................................................................................................... Page • • Updates were made in Section 6.1 ..................................................................................................... 8 Updates were made in Section 6.2. ...................................................................................................
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.