Datasheet

24
CC2650
SWRS158B –FEBRUARY 2015–REVISED JULY 2016 www.ti.com
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Specifications Copyright © 2015–2016, Texas Instruments Incorporated
5.22 Low-Power Clocked Comparator
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range 0 VDDS V
Clock frequency 32 kHz
Internal reference voltage, VDDS / 2 1.49 – 1.51 V
Internal reference voltage, VDDS / 3 1.01 – 1.03 V
Internal reference voltage, VDDS / 4 0.78 – 0.79 V
Internal reference voltage, DCOUPL / 1 1.25 – 1.28 V
Internal reference voltage, DCOUPL / 2 0.63 – 0.65 V
Internal reference voltage, DCOUPL / 3 0.42 – 0.44 V
Internal reference voltage, DCOUPL / 4 0.33 – 0.34 V
Offset <2 mV
Hysteresis <5 mV
Decision time Step from –50 mV to 50 mV <1 clock-cycle
Current consumption when enabled 362 nA
(1) Additionally, the bias module must be enabled when running in standby mode.
5.23 Programmable Current Source
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current source programmable output range 0.25 – 20 µA
Resolution 0.25 µA
Current consumption
(1)
Including current source at maximum
programmable output
23 µA
(1) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.
5.24 Synchronous Serial Interface (SSI)
T
c
= 25°C, V
DDS
= 3.0 V, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
S1
(1)
t
clk_per
(SSIClk period) Device operating as SLAVE 12 65024
system
clocks
S2
(1)
t
clk_high
(SSIClk high time) Device operating as SLAVE 0.5 t
clk_per
S3
(1)
t
clk_low
(SSIClk low time) Device operating as SLAVE 0.5 t
clk_per
S1 (TX only)
(1)
t
clk_per
(SSIClk period)
One-way communication to SLAVE -
Device operating as MASTER
4 65024
system
clocks
S1 (TX and RX)
(1)
t
clk_per
(SSIClk period)
Normal duplex operation - Device
operating as MASTER
8 65024
system
clocks
S2
(1)
t
clk_high
(SSIClk high time) Device operating as MASTER 0.5 t
clk_per
S3
(1)
t
clk_low
(SSIClk low time) Device operating as MASTER 0.5 t
clk_per