Datasheet

35
CC1350
www.ti.com SWRS183 –JUNE 2016
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Product Folder Links: CC1350
Detailed DescriptionCopyright © 2016, Texas Instruments Incorporated
(1) Not including RTOS overhead
6.7 Power Management
To minimize power consumption, the CC1350 supports a number of power modes and power-
management features (see Table 6-2).
Table 6-2. Power Modes
MODE
SOFTWARE CONFIGURABLE POWER MODES
RESET PIN
HELD
ACTIVE IDLE STANDBY SHUTDOWN
CPU Active Off Off Off Off
Flash On Available Off Off Off
SRAM On On On Off Off
Radio Available Available Off Off Off
Supply System On On Duty Cycled Off Off
Current 1.2 mA + 25.5 µA/MHz 570 µA 0.6 µA 185 nA 0.1 µA
Wake-up Time to CPU Active
(1)
– 14 µs 174 µs 1015 µs 1015 µs
Register Retention Full Full Partial No No
SRAM Retention Full Full Full No No
High-Speed Clock
XOSC_HF or
RCOSC_HF
XOSC_HF or
RCOSC_HF
Off Off Off
Low-Speed Clock
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
XOSC_LF or
RCOSC_LF
Off Off
Peripherals Available Available Off Off Off
Sensor Controller Available Available Available Off Off
Wake-up on RTC Available Available Available Off Off
Wake-up on Pin Edge Available Available Available Available Off
Wake-up on Reset Pin Available Available Available Available Available
Brown Out Detector (BOD) Active Active Duty Cycled Off N/A
Power On Reset (POR) Active Active Active Active N/A
In active mode, the application CM3 CPU is actively executing code. Active mode provides normal
operation of the processor and all of the peripherals that are currently enabled. The system clock can be
any available clock source (see Table 6-2).
In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not
clocked and no code is executed. Any interrupt event brings the processor back into active mode.
In standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or
Sensor Controller event is required to bring the device back to active mode. MCU peripherals with
retention do not need to be reconfigured when waking up again, and the CPU continues execution from
where it went into standby mode. All GPIOs are latched in standby mode.
In shutdown mode, the device is entirely turned off (including the AON domain and Sensor Controller),
and the I/Os are latched with the value they had before entering shutdown mode. A change of state on
any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger.
The CPU can differentiate between reset in this way and reset-by-reset pin or power-on-reset by reading
the reset status register. The only state retained in this mode is the latched I/O state and the flash memory
contents.
The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor
Controller independent of the main CPU. This means that the main CPU does not have to wake up, for
example to execute an ADC sample or poll a digital sensor over SPI, thus saving both current and wake-
up time that would otherwise be wasted. The Sensor Controller Studio lets the user configure the Sensor
Controller and choose which peripherals are controlled and which conditions wake up the main CPU.