Datasheet
40
39
DIO_24
38
37
21
22
23
24
DCDC_SW33
34
RESET_N35
DIO_2336
X32K_Q2
4
X32K_Q1
3
RF_N 2
RF_P 1
DIO_21
32
DIO_20
31
DIO_19
30
DIO_18
29
5
DIO_1 6
DIO_2 7
8
28
27
26
JTAG_TCKC25
9
10
11
12
41
42
43
44
20
DIO_14
19
DIO_13
18
17
VDDR 45
46
47
VDDR_RF 48
16
15
14
13
DIO_17
DIO_16
VDDS_DCDC
DIO_25
DIO_11
DIO_12
VDDS2
DIO_10
DIO_9
DIO_5
DIO_6
DIO_7
DIO_3
DIO_4
X24M_N
X24M_P
DIO_8
DIO_27
VDDS3
DCOUPL
JTAG_TMSC
DIO_28
DIO_26
VDDS
RX_TX
DIO_29
DIO_15
DIO_22
DIO_30
11
CC1310
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SWRS181C –SEPTEMBER 2015–REVISED OCTOBER 2016
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Terminal Configuration and FunctionsCopyright © 2015–2016, Texas Instruments Incorporated
4.5 Pin Diagram – RGZ Package
Figure 4-3 shows the RGZ pinout diagram.
Figure 4-3. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch
I/O pins marked in Figure 4-3 in bold have high-drive capabilities; they are as follows:
• Pin 10, DIO_5
• Pin 11, DIO_6
• Pin 12, DIO_7
• Pin 24, JTAG_TMSC
• Pin 26, DIO_16
• Pin 27, DIO_17
I/O pins marked in Figure 4-3 in italics have analog capabilities; they are as follows:
• Pin 36, DIO_23
• Pin 37, DIO_24
• Pin 38, DIO_25
• Pin 39, DIO_26
• Pin 40, DIO_27
• Pin 41, DIO_28
• Pin 42, DIO_29
• Pin 43, DIO_30