Datasheet

10
CC1310
SWRS181C –SEPTEMBER 2015–REVISED OCTOBER 2016 www.ti.com
Submit Documentation Feedback
Product Folder Links: CC1310
Terminal Configuration and Functions Copyright © 2015–2016, Texas Instruments Incorporated
(1) See the technical reference manual listed in Documentation Support for more details.
(2) Do not supply external circuitry from this pin.
(3) If internal DC-DC is not used, this pin is supplied internally from the main LDO.
(4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.
4.4 Signal Descriptions – RHB Package
Table 4-2. Signal Descriptions – RHB Package
PIN
TYPE DESCRIPTION
NAME NO.
DCDC_SW 17 Power Output from internal DC-DC
(1)
DCOUPL 12 Power 1.27-V regulated digital-supply decoupling
(2)
DIO_0 6 Digital I/O GPIO, Sensor Controller
DIO_1 7 Digital I/O GPIO, Sensor Controller
DIO_2 8 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_3 9 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_4 10 Digital I/O GPIO, Sensor Controller, high-drive capability
DIO_5 15 Digital I/O GPIO, high-drive capability, JTAG_TDO
DIO_6 16 Digital I/O GPIO, high-drive capability, JTAG_TDI
DIO_7 20 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_8 21 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_9 22 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_10 23 Digital or analog I/O GPIO, Sensor Controller, Analog
DIO_11 24 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_12 25 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_13 26 Digital or analog I/O GPIO, Sensor Controller, analog
DIO_14 27 Digital or analog I/O GPIO, Sensor Controller, analog
EGP – Power Ground; exposed ground pad
JTAG_TMSC 13 Digital I/O JTAG TMSC, high-drive capability
JTAG_TCKC 14 Digital I/O JTAG TCKC
RESET_N 19 Digital input Reset, active low. No internal pullup.
RF_N 2 RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal from PA during TX
RF_P 1 RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal from PA during TX
RX_TX 3 RF I/O Optional bias pin for the RF LNA
VDDR 29 Power 1.7-V to 1.95-V supply, connect to output of internal DC-DC
(2)(3)
VDDR_RF 32 Power 1.7-V to 1.95-V supply, connect to output of internal DC-DC
(2)(4)
VDDS 28 Power 1.8-V to 3.8-V main chip supply
(1)
VDDS2 11 Power 1.8-V to 3.8-V GPIO supply
(1)
VDDS_DCDC 18 Power 1.8-V to 3.8-V DC-DC supply
X24M_N 30 Analog I/O 24-MHz crystal oscillator pin 1
X24M_P 31 Analog I/O 24-MHz crystal oscillator pin 2
X32K_Q1 4 Analog I/O 32-kHz crystal oscillator pin 1
X32K_Q2 5 Analog I/O 32-kHz crystal oscillator pin 2