Datasheet

FAULT
ISO - Barrier
DELAY
GND1
V
IN+
V
IN-
V
CC1
FAULT
RESET
ISO5500
3.3V
µC
I/P
O/P
PWM
S
R
Q
R
PU
ISO
V
IN+
ISO
FAULT
FAULT
RESET
DIS
DIS
D
e
l
a
y
S
h
o
r
t
o
c
c
u
r
s
1
2
3
4
5
6
“IGBT
On”
ISO5500
www.ti.com SLLSE64C –SEPTEMBER 2011–REVISED JUNE 2013
The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault
condition. The use of V
IN+
as control input implies non-inverting input configuration.
During normal operation V
DESAT
will display a small sawtooth waveform every time V
IN+
goes high. The ramp of
the sawtooth is caused by the internal current source charging the blanking capacitor. Once the IGBT collector
has sufficiently dropped below the capacitor voltage, the DESAT diode conducts and discharges C
BLK
through
the IGBT.
In the event of a short circuit fault; however, high IGBT collector voltage prevents the diode from conducting and
the voltage at the blanking capacitor continues to rise until it reaches the DESAT threshold. When the output of
the DESAT comparator goes high, the gate-drive and fault-logic circuit initiates the soft shutdown sequence and
also produces a Fault signal that is fed back to the input side of the ISO5500.
FAULT ALARM
The Fault alarm unit consists of three circuit elements, a RS flip-flop to store the fault signal received from the
gate-drive and fault-logic, an open-drain MOSFET output signaling the fault condition to the micro controller, and
a delay circuit blocking the control inputs after the soft shutdown sequence of the IGBT has been completed.
Figure 60 shows the ISO5500 in a non-inverting input configuration. Because the FAULT-pin is an open-drain
output, it requires a pull-up resistor, R
PU
, in the order of 3.3 kΩ to 10 kΩ. The internal signals DIS, ISO, and
FAULT represent the input-disable signal, the isolator output signal, and the fault feedback signal respectively.
Figure 60. Fault Alarm Circuitry and Timing Sequence
The timing diagram shows that the micro controller initiates an IGBT-on command by taking V
IN+
high. After
propagating across the isolation barrier ISO goes high, activating the output stage.
1. Upon a short circuit condition the gate-drive and fault-logic feeds back a fault signal (FAULT = high) which
sets the RS-FF driving the FAULT output active-low.
2. After a delay of approximately 3 μs, the time required to shutdown the IGBT, DIS becomes high and blocks
the control inputs
3. This in turn drives ISO low
4. which, after propagating through the output fault-logic, drives FAULT low.
At this time both flip-flop inputs are low and the fault signal is stored.
5. Once the failure cause has been removed the micro controller must set the control inputs into an "Output-
low" state before applying the Reset pulse.
6. Taking the RESET-input low resets the flip-flop, which removes the fault signal from the controller by pulling
FAULT high and releases the control inputs by driving DIS low
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