Datasheet

V
C
V
CC2
15V
Q1a
Q1b
Q2aQ2b
Q3
V
OUT
V
EE-P
V
E
On
Off
Slow
Off
15V
ISO5500
V
GE
V
E
V
IN+
V
OUT
V
GE
0V
30V
-15V
+15V
V
E
Q1 Q2 Q1
Q2
Q3
Gate
Drive
V
EE-L
ISO5500
SLLSE64C –SEPTEMBER 2011–REVISED JUNE 2013 www.ti.com
OUTPUT STAGE
The output stage provides the actual IGBT gate drive by switching the output voltage pin, V
OUT
, between the
most positive potential, typically V
CC2
, and the most negative potential, V
EE-P
.
Figure 57. Output Stage Design and Timing
This stage consists of an upper transistor pair (Q1a and Q1b) turning the IGBT on, and a lower transistor pair
(Q2a and Q2b) turning the IGBT off. Each transistor pair possesses a bipolar transistor for high current drive and
a MOSFET for close-to-rail switching capability.
An additional, weak MOSFET (Q3) is used to softly turn-off the IGBT in the event of a short circuit fault to
prevent large di/dt voltage transients which potentially could damage the output circuitry.
The output control signals, On, Off, and Slow-Off are provided by the gate-drive and fault-logic circuit which also
includes a break-before-make function to prevent both transistor pairs from conducting at the same time.
By introducing the reference potential for the IGBT emitter, V
E
, the final IGBT gate voltage, V
GE
, assumes
positive and negative values with respect to V
E
.
A positive V
GE
of typically 15 V is required to switch the IGBT well into saturation while assuring the survival of
short circuit currents of up to 5–10 times the rated collector current over a time span of up to 10 μs.
Negative values of V
E
, ranging from a required minimum of –5 V up to a recommended –15 V, are necessary to
keep the IGBT turned off and to prevent it from unintentional conducting due to noise transients, particularly
during short circuit faults. As previously mentioned, MOSFETs do not require a negative gate-voltage and thus
allow the V
E
-pin to be directly connected to V
EE-P
.
The timing diagram in Figure 57 shows that during normal operation V
OUT
follows the switching sequence of V
IN+
(here shown for the non-inverting input configuration), and only the Q1 and Q2 transistor pairs applying V
CC2
and
V
EE-P
potential to the V
OUT
-pin respectively.
In the event of a short circuit fault, however, while the IGBT is actively driven, the Q1 pair is turned off and Q3
turns on to slowly reduce V
OUT
in a controlled manner down to a level of approximately 2 V above V
EE-P
. At this
voltage level, the strong Q2 pair then conducts holding V
OUT
at V
EE-P
potential.
UNDER VOLTAGE LOCKOUT (UVLO)
The Under Voltage Lockout feature prevents the application of insufficient gate voltage (V
GE-ON
) to the power
device by forcing V
OUT
low (V
OUT
= V
EE-P
) during power-up and whenever else V
CC2
– V
E
drops below 12.3 V.
IGBTs and MOSFETs typically require gate voltages of V
GE
= 15 V to achieve their rated, low saturation voltage,
V
CES
. At gate voltages below 13 V typically, their V
CE-ON
increases drastically, especially at higher collector
currents. At even lower voltages, i.e. V
GE
< 10 V, an IGBT starts operating in the linear region and quickly
overheats. Figure 58 shows the principle operation of the UVLO feature.
22 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links :ISO5500