Datasheet
V
IN+
V
DESAT
V
OUT
FAULT
RESET
7.2V
ISO
FAULT
DIS
Normal Operation Fault Condition Reset Normal Operation
D
e
l
a
y
2
3
4
1
5
6
270 μA
+
-
+
-
12.3V
FAULT
ISO - Barrie r
DELAY
ISO
UVLO
Q1a
Q1b
Q2aQ2b
Q3
S
R
Q
GND1
V
IN+
V
IN-
V
CC1
V
C
V
OUT
V
EE-P
DESAT
V
CC2
V
E
FAULT
RESET
VREG V
CC2
VREG
ISO5500
15V
C
BLK
7.2V
+HV
LOAD
-HV
I/P
O/P
PWM
μC
V
EE-L
10,15
9
16
11
12
13
14
4,8
5
6
3
2
1
DIS
3.3V
to
5V
15V
ISO5500
SLLSE64C –SEPTEMBER 2011–REVISED JUNE 2013
www.ti.com
BEHAVIORAL MODEL
Figure 53 and Figure 54 show the detailed behavioral model of the ISO5500 for a non-inverting input
configuration and its corresponding timing diagram for normal operation, fault condition, and Reset.
Figure 53. ISO5500 Behavioral Model
Figure 54. Complete Timing Diagram
20 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links :ISO5500