Datasheet

+
-
+
-
ISO - Barri er
DELAY
GND1
V
IN+
V
IN-
V
CC1
V
C
DESAT
V
CC2
FAULT
ISO5500
VREG
UVLO
DESAT
Gate
Drive
and
Fault
Logic
7.2V
12.3V
Q1a
Q1b
Q2aQ2b
Q3
V
OUT
V
EE-P
V
E
S
R
Q
V
EE-L
RESET
Q4
ISO5500
SLLSE64C –SEPTEMBER 2011–REVISED JUNE 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
FUNCTION TABLE
UVLO DESAT DETECTED ON PIN 6 (FAULT)
V
IN
+ V
IN
- V
OUT
(V
CC2
– V
E
) PIN 14 (DESAT) OUTPUT
X X Active X X Low
X X X Yes Low Low
Low X X X X Low
X High X X X Low
High Low Not active No High High
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