Datasheet

0 or
I
I
V
I
V
CC1
DE
A
B
V
OB
V
OA
V
OD
I
OA
I
OB
GND1
GND1
GND2
V
CC1
GND2
375 W
60 W
+
V
OD
–
D
DE
GND 2
V
CC2
A
B
0 V or 3 V
375 W
–7 V to 12 V
ISO3080, ISO3086
ISO3082, ISO3088
SLOS581E – MAY 2008–REVISED SEPTEMBER 2011 www.ti.com
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IT(+)
Positive-going input threshold voltage I
O
= –8 mA –85 –10 mV
V
IT(–)
Negative-going input threshold voltage I
O
= 8 mA –200 –115 mV
V
hys
Hysteresis voltage (V
IT+
– V
IT–
) 30 mV
3.3-V V
CC1
V
CC1
-0.4 3.1
V
ID
= 200 mV, I
O
= –8 mA,
V
OH
High-level output voltage V
See Figure 7
5-V V
CC1
4 4.8
3.3-V V
CC1
0.15 0.4
V
ID
= –200 mV, I
O
= 8 mA,
V
OL
Low-level output voltage V
See Figure 7
5-V V
CC1
0.15 0.4
I
O(Z)
High-impedance state output current V
I
= –7 to 12 V, Other input = 0 V –1 1 μA
V
A
or V
B
= 12 V 0.04 0.1
V
A
or V
B
= 12 V, V
CC
= 0 0.06 0.13
Other input
I
I
Bus input current mA
at 0 V
V
A
or V
B
= –7 V –0.1 –0.04
V
A
or V
B
= –7 V, V
CC
= 0 –0.05 –0.03
I
IH
High-level input current, RE V
IH
= 2 V –10 10 μA
I
IL
Low-level input current, RE V
IL
= 0.8 V –10 10 μA
R
ID
Differential input resistance A, B 48 kΩ
Test input signal is a 1.5 MHz sine wave with 1Vpp
C
D
Differential input capacitance 7 pF
amplitude. CD is measured across A and B.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
, t
PHL
Propagation delay 90 125
ns
PWD
(1)
Pulse width distortion |t
PHL
– t
PLH
| See Figure 8 4 12
t
r
, t
f
Output signal rise and fall time 1 ns
t
PHZ
, Propagation delay, high-level-to-high-impedance output
See Figure 9, DE at 0 V 22 ns
t
PZH
Propagation delay, high-impedance-to-high-level output
t
PZL
, Propagation delay, high-impedance-to-low-level output
See Figure 10, DE at 0 V 22 ns
t
PLZ
Propagation delay, low-level-to-high-impedance output
(1) Also known as pulse skew.
PARAMETER MEASUREMENT INFORMATION
Figure 1. Driver V
OD
Test and Current Definitions Figure 2. Driver V
OD
With Common-Mode Loading
Test Circuit
Note: Unless otherwise stated, test circuits are shown for half-duplex devices, ISO3082 & ISO3088. For
full-duplex devices, driver output pins are Y and Z.
4 Submit Documentation Feedback Copyright © 2008–2011, Texas Instruments Incorporated
Product Folder Link(s): ISO3080, ISO3086 ISO3082, ISO3088