Datasheet

ISO1050
www.ti.com SLLS983H –JUNE 2009–REVISED JUNE 2013
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
(1)
MAX UNIT
V
IT+
Positive-going bus input threshold voltage 750 900 mV
See Table 4
V
IT–
Negative-going bus input threshold voltage 500 650 mV
V
hys
Hysteresis voltage (V
IT+
– V
IT–
) 150 mV
I
OH
= –4 mA, See Figure 9 V
CC
– 0.8 4.6
V
OH
High-level output voltage with Vcc = 5V V
I
OH
= –20 μA, See Figure 9 V
CC
– 0.1 5
I
OL
= 4 mA, See Figure 9 V
CC
– 0.8 3.1
V
OH
High-level output voltage with Vcc1 = 3.3V V
I
OL
= 20 μA, See Figure 9 V
CC
– 0.1 3.3
I
OL
= 4 mA, See Figure 9 0.2 0.4
V
OL
Low-level output voltage V
I
OL
= 20 μA, See Figure 9 0 0.1
C
I
Input capacitance to ground, (CANH or CANL) TXD at 3 V, V
I
= 0.4 sin (4E6πt) + 2.5V 6 pF
C
ID
Differential input capacitance TXD at 3 V, V
I
= 0.4 sin (4E6πt) 3 pF
R
ID
Differential input resistance TXD at 3 V 30 80 kΩ
R
IN
Input resistance (CANH or CANL) TXD at 3 V 15 30 40 kΩ
Input resistance matching
R
I(m)
V
CANH
= V
CANL
–3% 0% 3%
(1 – [R
IN (CANH)
/ R
IN (CANL)
]) × 100%
CMTI Common-mode transient immunity V
I
= V
CC
or 0 V, See Figure 16 25 50 kV/μs
(1) All typical values are at 25°C with V
CC1
= V
CC2
= 5V.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
Propagation delay time, low-to-high-level output 66 90 130
t
PHL
Propagation delay time, high-to-low-level output 51 80 105
TXD at 3 V, See Figure 9 ns
t
r
Output signal rise time 3 6
t
f
Output signal fall time 3 6
t
fs
Failsafe output delay time from bus-side power loss VCC1 at 5 V, See Figure 15 6 μs
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